On Thu, May 21, 2020 at 10:16:36AM -0500, Suman Anna wrote: > The Texas Instrument's K3 J721E SoCs have a newer next-generation > C71x DSP Subsystem in the MAIN voltage domain in addition to the > previous generation C66x DSP subsystems. The C71x DSP subsystem is > based on the TMS320C71x DSP CorePac module. The C71x CPU is a true > 64-bit machine including 64-bit memory addressing and single-cycle > 64-bit base arithmetic operations and supports vector signal processing > providing a significant lift in DSP processing power over C66x DSPs. > J721E SoCs use a C711 (a one-core 512-bit vector width CPU core) DSP > that is cache coherent with the A72 Arm cores. > > Each subsystem has one or more Fixed/Floating-Point DSP CPUs, with 32 KB > of L1P Cache, 48 KB of L1D SRAM that can be configured and partitioned as > either RAM and/or Cache, and 512 KB of L2 SRAM configurable as either RAM > and/or Cache. The CorePac also includes a Matrix Multiplication Accelerator > (MMA), a Stream Engine (SE) and a C71x Memory Management Unit (CMMU), an > Interrupt Controller (INTC) and a Powerdown Management Unit (PMU) modules. > > Update the existing K3 DSP remoteproc driver to add support for this C71x > DSP subsystem. The firmware loading support is provided by using the newly > added 64-bit ELF loader support, and is limited to images using only > external DDR memory at the moment. The L1D and L2 SRAMs are used as scratch > memory when using as RAMs, and cannot be used for loadable segments. The > CMMU is also not supported to begin with, and the driver is designed to > treat the MMU as if it is in bypass mode. > > Signed-off-by: Suman Anna <s-anna@xxxxxx> > --- > v2: > - k3_dsp_rproc_prepare/unprepare plugged in dynamically based on local reset, > C71x doesn't use local resets > - Dropped the sanity_check ops override, not needed on latest codebase > v1: https://patchwork.kernel.org/patch/11458595/ > > drivers/remoteproc/ti_k3_dsp_remoteproc.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/remoteproc/ti_k3_dsp_remoteproc.c b/drivers/remoteproc/ti_k3_dsp_remoteproc.c > index 610fbbf85ee6..2dbed316b6ac 100644 > --- a/drivers/remoteproc/ti_k3_dsp_remoteproc.c > +++ b/drivers/remoteproc/ti_k3_dsp_remoteproc.c > @@ -406,8 +406,6 @@ static void *k3_dsp_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) > } > > static const struct rproc_ops k3_dsp_rproc_ops = { > - .prepare = k3_dsp_rproc_prepare, > - .unprepare = k3_dsp_rproc_unprepare, > .start = k3_dsp_rproc_start, > .stop = k3_dsp_rproc_stop, > .kick = k3_dsp_rproc_kick, > @@ -617,6 +615,10 @@ static int k3_dsp_rproc_probe(struct platform_device *pdev) > > rproc->has_iommu = false; > rproc->recovery_disabled = true; > + if (data->uses_lreset) { > + rproc->ops->prepare = k3_dsp_rproc_prepare; > + rproc->ops->unprepare = k3_dsp_rproc_unprepare; > + } Yes > kproc = rproc->priv; > kproc->rproc = rproc; > kproc->dev = dev; > @@ -744,6 +746,12 @@ static const struct k3_dsp_mem_data c66_mems[] = { > { .name = "l1dram", .dev_addr = 0xf00000 }, > }; > > +/* C71x cores only have a L1P Cache, there are no L1P SRAMs */ > +static const struct k3_dsp_mem_data c71_mems[] = { > + { .name = "l2sram", .dev_addr = 0x800000 }, > + { .name = "l1dram", .dev_addr = 0xe00000 }, > +}; > + > static const struct k3_dsp_dev_data c66_data = { > .mems = c66_mems, > .num_mems = ARRAY_SIZE(c66_mems), > @@ -751,8 +759,16 @@ static const struct k3_dsp_dev_data c66_data = { > .uses_lreset = true, > }; > > +static const struct k3_dsp_dev_data c71_data = { > + .mems = c71_mems, > + .num_mems = ARRAY_SIZE(c71_mems), > + .boot_align_addr = SZ_2M, > + .uses_lreset = false, Right > +}; > + > static const struct of_device_id k3_dsp_of_match[] = { > { .compatible = "ti,j721e-c66-dsp", .data = &c66_data, }, > + { .compatible = "ti,j721e-c71-dsp", .data = &c71_data, }, > { /* sentinel */ }, > }; Reviewed-by: Mathieu Poirier <mathieu.poirier@xxxxxxxxxx> > MODULE_DEVICE_TABLE(of, k3_dsp_of_match); > -- > 2.26.0 >
