On Thu, May 21, 2020 at 05:07:15PM +0300, Serge Semin wrote: > This is a MIPS32 Release 5 based IP core with XPA, EVA, dual/quad issue > exec pipes, MMU with two-levels TLB, UCA, MSA, MDU core level features > and system level features like up to six P5600 calculation cores, CM2 > with L2 cache, IOCU/IOMMU (though might be unused depending on the > system-specific IP core configuration), GIC, CPC, virtualisation module, > eJTAG and PDtrace. > > As being MIPS32 Release 5 based core it provides all the features > available by the CPU_MIPS32_R5 config, while adding a few more like > UCA attribute support, availability of CPU-freq (by means of L2/CM > clock ratio setting), EI/VI GIC modes detection at runtime. > > In addition to this if P5600 architecture is enabled modern GNU GCC > provides a specific tuning for P5600 processors with respect to the > classic MIPS32 Release 5. First of all branch-likely avoidance is > activated only when the code is compiled with the speed optimization > (avoidance is always enabled for the pure MIPS32 Release 5 > architecture). Secondly the madd/msub avoidance is enabled since > madd/msub utilization isn't profitable due to overhead of getting the > result out of the HI/LO registers. Multiply-accumulate instructions are > activated and utilized together with the necessary code reorder when > multiply-add/multiply-subtract statements are met. Finally load/store > bonding is activated by default. All of these optimizations may make > the code relatively faster than if just MIP32 release 5 architecture > was requested. > > Co-developed-by: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > Cc: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx> > Cc: Paul Burton <paulburton@xxxxxxxxxx> > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > Cc: Arnd Bergmann <arnd@xxxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > --- > arch/mips/Kconfig | 37 +++++++++++++++++++++++++++++----- > arch/mips/Makefile | 1 + > arch/mips/include/asm/module.h | 2 ++ > 3 files changed, 35 insertions(+), 5 deletions(-) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
