On 20/12/2019 08:26, Andrew-sh.Cheng wrote: > From: "Andrew-sh.Cheng" <andrew-sh.cheng@xxxxxxxxxxxx> > > add cpufreq and cci devfreq nodes for mt8183 > > Depend on regulator node patch: > https://patchwork.kernel.org/patch/11284617/ > > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@xxxxxxxxxxxx> > --- Now queued for v5.7-next/dts64 Thanks! > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 245 ++++++++++++++++++++++++++++ > 2 files changed, 281 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > index 1fb195c..ca5c0b2 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -231,6 +231,42 @@ > > }; > > +&cci { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu0 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu1 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu2 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu3 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu4 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > +&cpu5 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > +&cpu6 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > +&cpu7 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > &uart0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 10b3247..d260a5a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -31,6 +31,219 @@ > i2c11 = &i2c11; > }; > > + cluster0_opp: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00 { > + opp-hz = /bits/ 64 <793000000>; > + opp-microvolt = <650000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <910000000>; > + opp-microvolt = <687500>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <1014000000>; > + opp-microvolt = <718750>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <1131000000>; > + opp-microvolt = <756250>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <1248000000>; > + opp-microvolt = <800000>; > + }; > + opp05 { > + opp-hz = /bits/ 64 <1326000000>; > + opp-microvolt = <818750>; > + }; > + opp06 { > + opp-hz = /bits/ 64 <1417000000>; > + opp-microvolt = <850000>; > + }; > + opp07 { > + opp-hz = /bits/ 64 <1508000000>; > + opp-microvolt = <868750>; > + }; > + opp08 { > + opp-hz = /bits/ 64 <1586000000>; > + opp-microvolt = <893750>; > + }; > + opp09 { > + opp-hz = /bits/ 64 <1625000000>; > + opp-microvolt = <906250>; > + }; > + opp10 { > + opp-hz = /bits/ 64 <1677000000>; > + opp-microvolt = <931250>; > + }; > + opp11 { > + opp-hz = /bits/ 64 <1716000000>; > + opp-microvolt = <943750>; > + }; > + opp12 { > + opp-hz = /bits/ 64 <1781000000>; > + opp-microvolt = <975000>; > + }; > + opp13 { > + opp-hz = /bits/ 64 <1846000000>; > + opp-microvolt = <1000000>; > + }; > + opp14 { > + opp-hz = /bits/ 64 <1924000000>; > + opp-microvolt = <1025000>; > + }; > + opp15 { > + opp-hz = /bits/ 64 <1989000000>; > + opp-microvolt = <1050000>; > + }; }; > + > + cluster1_opp: opp_table1 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00 { > + opp-hz = /bits/ 64 <793000000>; > + opp-microvolt = <700000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <910000000>; > + opp-microvolt = <725000>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <1014000000>; > + opp-microvolt = <750000>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <1131000000>; > + opp-microvolt = <775000>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <1248000000>; > + opp-microvolt = <800000>; > + }; > + opp05 { > + opp-hz = /bits/ 64 <1326000000>; > + opp-microvolt = <825000>; > + }; > + opp06 { > + opp-hz = /bits/ 64 <1417000000>; > + opp-microvolt = <850000>; > + }; > + opp07 { > + opp-hz = /bits/ 64 <1508000000>; > + opp-microvolt = <875000>; > + }; > + opp08 { > + opp-hz = /bits/ 64 <1586000000>; > + opp-microvolt = <900000>; > + }; > + opp09 { > + opp-hz = /bits/ 64 <1625000000>; > + opp-microvolt = <912500>; > + }; > + opp10 { > + opp-hz = /bits/ 64 <1677000000>; > + opp-microvolt = <931250>; > + }; > + opp11 { > + opp-hz = /bits/ 64 <1716000000>; > + opp-microvolt = <950000>; > + }; > + opp12 { > + opp-hz = /bits/ 64 <1781000000>; > + opp-microvolt = <975000>; > + }; > + opp13 { > + opp-hz = /bits/ 64 <1846000000>; > + opp-microvolt = <1000000>; > + }; > + opp14 { > + opp-hz = /bits/ 64 <1924000000>; > + opp-microvolt = <1025000>; > + }; > + opp15 { > + opp-hz = /bits/ 64 <1989000000>; > + opp-microvolt = <1050000>; > + }; > + }; > + > + cci_opp: opp_table2 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00 { > + opp-hz = /bits/ 64 <273000000>; > + opp-microvolt = <650000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <338000000>; > + opp-microvolt = <687500>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <403000000>; > + opp-microvolt = <718750>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <463000000>; > + opp-microvolt = <756250>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <546000000>; > + opp-microvolt = <800000>; > + }; > + opp05 { > + opp-hz = /bits/ 64 <624000000>; > + opp-microvolt = <818750>; > + }; > + opp06 { > + opp-hz = /bits/ 64 <689000000>; > + opp-microvolt = <850000>; > + }; > + opp07 { > + opp-hz = /bits/ 64 <767000000>; > + opp-microvolt = <868750>; > + }; > + opp08 { > + opp-hz = /bits/ 64 <845000000>; > + opp-microvolt = <893750>; > + }; > + opp09 { > + opp-hz = /bits/ 64 <871000000>; > + opp-microvolt = <906250>; > + }; > + opp10 { > + opp-hz = /bits/ 64 <923000000>; > + opp-microvolt = <931250>; > + }; > + opp11 { > + opp-hz = /bits/ 64 <962000000>; > + opp-microvolt = <943750>; > + }; > + opp12 { > + opp-hz = /bits/ 64 <1027000000>; > + opp-microvolt = <975000>; > + }; > + opp13 { > + opp-hz = /bits/ 64 <1092000000>; > + opp-microvolt = <1000000>; > + }; > + opp14 { > + opp-hz = /bits/ 64 <1144000000>; > + opp-microvolt = <1025000>; > + }; > + opp15 { > + opp-hz = /bits/ 64 <1196000000>; > + opp-microvolt = <1050000>; > + }; > + }; > + > + cci: cci { > + compatible = "mediatek,mt8183-cci"; > + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; > + clock-names = "cci_clock"; > + operating-points-v2 = <&cci_opp>; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -73,6 +286,10 @@ > reg = <0x000>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu1: cpu@1 { > @@ -81,6 +298,10 @@ > reg = <0x001>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu2: cpu@2 { > @@ -89,6 +310,10 @@ > reg = <0x002>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu3: cpu@3 { > @@ -97,6 +322,10 @@ > reg = <0x003>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu4: cpu@100 { > @@ -105,6 +334,10 @@ > reg = <0x100>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > > cpu5: cpu@101 { > @@ -113,6 +346,10 @@ > reg = <0x101>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > > cpu6: cpu@102 { > @@ -121,6 +358,10 @@ > reg = <0x102>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > > cpu7: cpu@103 { > @@ -129,6 +370,10 @@ > reg = <0x103>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > }; > >
