On Thu, May 21, 2020 at 03:34:37AM +0300, Serge Semin wrote: > Indeed according to the MIPS32 Privileged Resource Architecgture the MAAR > pair register address field either takes [12:31] bits for non-XPA systems > and [12:55] otherwise. In any case the current address mask is just > wrong for 64-bit and 32-bits XPA chips. So lets extend it to 59-bits > of physical address value. This shall cover the 64-bits architecture and > systems with XPA enabled, and won't cause any problem for non-XPA 32-bit > systems, since address values exceeding the architecture specific MAAR > mask will be just truncated with setting zeros in the unsupported upper > bits. > > Co-developed-by: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > Cc: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx> > Cc: Paul Burton <paulburton@xxxxxxxxxx> > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > Cc: Arnd Bergmann <arnd@xxxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > > --- > > Changelog v3: > - In accordance with MIPS32/64 Privileged Resource Architecture Extend > the MAAR Addr mask to value [12:55] instead of P5600-specific [12:35]. > --- > arch/mips/include/asm/mipsregs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
