This patch adds device tree bindings for the Microchip PCIe PolarFire PCIe controller when configured in host (Root Complex) mode. Signed-off-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> --- .../bindings/pci/microchip,pcie-host.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml new file mode 100644 index 000000000000..d3bcdab282c2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PCIe Root Port Bridge Controller + +maintainers: + - Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: microchip,pcie-host-1.0 # PolarFire + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: apb + + interrupts: + minItems: 1 + maxItems: 1 + items: + - description: PCIe host controller and builtin MSI controller + + interrupt-names: + minItems: 1 + maxItems: 1 + items: + - const: pcie/msi + + ranges: + maxItems: 1 + + dma-ranges: + maxItems: 1 + + msi-controller: + description: Identifies the node as an MSI controller. + + msi-parent: + description: MSI controller the device is capable of using. + +required: + - reg + - reg-names + - dma-ranges + - "#interrupt-cells" + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + - msi-controller + +examples: + - | + soc { + pcie0: pcie@2030000000 { + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + compatible = "microchip,pcie-host-1.0"; + device_type = "pci"; + bus-range = <0x00 0x7f>; + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(1) + interrupt-map = <0 0 0 1 &pcie0 0>, + <0 0 0 2 &pcie0 1>, + <0 0 0 3 &pcie0 2>, + <0 0 0 4 &pcie0 3>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&plic0>; + interrupts = <32>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x03000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x20 0x30000000 0x0 0x4000000>, + <0x20 0x0 0x0 0x100000>; + reg-names = "cfg", "apb"; + msi-parent = <&pcie0>; + msi-controller; + interrupt-controller; + }; + }; +... -- 2.17.1
