Rob, Could you take a look at this patch? Since you've accepted and merged in the patch: https://lore.kernel.org/linux-devicetree/20200506174238.15385-4-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ It's safe to perform the dt_binding_check of this one. -Sergey On Fri, May 08, 2020 at 02:07:03AM +0300, Serge Semin wrote: > There is a single register provided by the SoC system controller, > which can be used to tune the L2-cache RAM up. It only provides a way > to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" > compatible string the device node can be optionally equipped with the > properties of Tag/Data/WS latencies. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > Cc: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx> > Cc: Paul Burton <paulburton@xxxxxxxxxx> > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > Cc: Olof Johansson <olof@xxxxxxxxx> > Cc: Boris Brezillon <bbrezillon@xxxxxxxxxx> > Cc: Paul Cercueil <paul@xxxxxxxxxxxxxxx> > Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Cc: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> > Cc: linux-mips@xxxxxxxxxxxxxxx > Cc: soc@xxxxxxxxxx > > --- > > Changelog v2: > - Move driver to the memory subsystem. > - Use dual GPL/BSD license. > - Use single lined copyright header. > - Move "allOf" restrictions to the root level of the properties. > - Discard syscon compatible string and reg property. > - The DT node is supposed to be a child of the Baikal-T1 system controller > node. > --- > .../memory-controllers/baikal,bt1-l2-ctl.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml > new file mode 100644 > index 000000000000..263f0cdab4e6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Baikal-T1 L2-cache Control Block > + > +maintainers: > + - Serge Semin <fancer.lancer@xxxxxxxxx> > + > +description: | > + By means of the System Controller Baikal-T1 SoC exposes a few settings to > + tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible > + to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 > + L2-cache controller block is responsible for the tuning. Its DT node is > + supposed to be a child of the system controller. > + > +properties: > + compatible: > + const: baikal,bt1-l2-ctl > + > + baikal,l2-ws-latency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Cycles of latency for Way-select RAM accesses > + default: 0 > + minimum: 0 > + maximum: 3 > + > + baikal,l2-tag-latency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Cycles of latency for Tag RAM accesses > + default: 0 > + minimum: 0 > + maximum: 3 > + > + baikal,l2-data-latency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Cycles of latency for Data RAM accesses > + default: 1 > + minimum: 0 > + maximum: 3 > + > +additionalProperties: false > + > +required: > + - compatible > + > +examples: > + - | > + l2_ctl { > + compatible = "baikal,bt1-l2-ctl"; > + > + baikal,l2-ws-latency = <0>; > + baikal,l2-tag-latency = <0>; > + baikal,l2-data-latency = <1>; > + }; > +... > -- > 2.25.1 >
