[Sorry about the slight delay on getting back on this]
On 14/05/20 11:25, Mark Brown wrote:
> Date: Thu, 14 May 2020 11:25:16 +0100
> From: Mark Brown <broonie@xxxxxxxxxx>
> To: Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx>
> Cc: SoC Team <soc@xxxxxxxxxx>, Microchip Linux Driver Support
> <UNGLinuxDriver@xxxxxxxxxxxxx>, linux-spi@xxxxxxxxxxxxxxx,
> devicetree@xxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx,
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, Alexandre Belloni
> <alexandre.belloni@xxxxxxxxxxx>
> Subject: Re: [PATCH 07/10] spi: spi-dw-mchp: Add Sparx5 support
> User-Agent: Mutt/1.10.1 (2018-07-13)
>
> On Wed, May 13, 2020 at 04:00:28PM +0200, Lars Povlsen wrote:
>
> > +static void dw_spi_mchp_set_cs_owner(struct dw_spi_mchp *dwsmchp,
> > + const struct dw_spi_mchp_props *props,
> > + u8 cs, u8 owner)
> > {
> > + u8 dummy = (owner == MSCC_IF_SI_OWNER_SIBM ?
> > + MSCC_IF_SI_OWNER_SIMC : MSCC_IF_SI_OWNER_SIBM);
>
> Please write normal conditional statements to improve legibility.
>
I will take your recommendation to heart.
> > +static void dw_spi_mchp_set_cs(struct spi_device *spi, bool nEnable)
> > +{
> > + bool enable = !nEnable; /* This keeps changing in the API... */
>
> No, it doesn't. The API has not changed for more than a decade.
>
I will remove the comment.
I think the comment was related to when we got bitten by the below
change, but alas.
commit ada9e3fcc175db4538f5b5e05abf5dedf626e550
Author: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx>
Date: Wed Nov 27 15:39:36 2019 +0000
spi: dw: Correct handling of native chipselect
This patch reverts commit 6e0a32d6f376 ("spi: dw: Fix default polarity
of native chipselect").
> > + } else if (props->ss_force_ena_off) {
> > + if (enable) {
> > + /* Ensure CS toggles, so start off all disabled */
> > + regmap_write(dwsmchp->syscon, props->ss_force_val_off,
> > + ~0);
>
> What's all this force_ena_off stuff about? The controller should not be
> making decisions about management of the chip select, this will break
> users.
>
Our controller is not using DMA, but the FIFO interface. And as the DW
controller drops CS when the FIFO runs empty, this will upset SPI
devices. The "ss_force" is something the HW designes put on top to
"override" the CS. We could of course use the GPIO's specifically to
overcome this - but the "boot" CS 0 is a builtin CS, with no
underlying GPIO.
Add to this that the HW dept decided to add *2* physical SPI busses to
the same controller. That we also need to switch between. And ensure
CS gets dropped correctly before changing tracks...
Long story, lot of grief...
> > + if (pdev->dev.of_node) {
> > + int i;
> > +
> > + for (i = 0; i < dws->num_cs; i++) {
> > + int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
> > + "cs-gpios", i);
> > +
> > + if (cs_gpio == -EPROBE_DEFER) {
> > + ret = cs_gpio;
> > + goto out;
> > + }
> > +
> > + if (gpio_is_valid(cs_gpio)) {
> > + ret = devm_gpio_request(&pdev->dev, cs_gpio,
> > + dev_name(&pdev->dev));
> > + if (ret)
> > + goto out;
>
> Set use_gpio_descriptors and let the core manage the GPIO.
Good suggestion, just the ticket!
And thank you very much for your time & comments.
---Lars
