On Fri, May 15, 2020 at 10:40:58PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 01:47:41PM +0300, Serge Semin wrote:
> > > Since DMA transfers are performed asynchronously with actual SPI
> > > transaction, then even if DMA transfers are finished it doesn't mean
> > > all data is actually pushed to the SPI bus. Some data might still be
> > > in the controller FIFO. This is specifically true for Tx-only
> > > transfers. In this case if the next SPI transfer is recharged while
> > > a tail of the previous one is still in FIFO, we'll loose that tail
> > > data. In order to fix this lets add the wait procedure of the Tx/Rx
> > > SPI transfers completion after the corresponding DMA transactions
> > > are finished.
...
> > You forgot a Fixes tag.
>
> If you find a commit this patch fixes I'd be glad to add the tag.)
I believe you can do it, but I will help you here, what about
7063c0d942a1 ("spi/dw_spi: add DMA support")
or may be more closer to the reality
30c8eb52cc4a ("spi: dw-mid: split rx and tx callbacks when DMA")
?
...
> I will if v3 is needed.
I guess it will be due to Fixes tag.
--
With Best Regards,
Andy Shevchenko
