From: "Vineetha G. Jaya Kumaran" <vineetha.g.jaya.kumaran@xxxxxxxxx> Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC. Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@xxxxxxxxx> --- .../devicetree/bindings/pwm/pwm-keembay.yaml | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-keembay.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-keembay.yaml b/Documentation/devicetree/bindings/pwm/pwm-keembay.yaml new file mode 100644 index 0000000..00968d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-keembay.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@xxxxxxxxx> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + description: + phandle to the reference clock. + +required: + - compatible + - reg + - clocks + +examples: + - | + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x0 0x203200a0 0x0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + }; -- 1.9.1
