Hi Mike,
On 2020/4/16 4:12, Mike Leach wrote:
> Adds in CTI device tree information for the Hikey620 board.
>
> Tested on Linux 5.7-rc1.
>
> Signed-off-by: Mike Leach <mike.leach@xxxxxxxxxx>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@xxxxxxxxxx>
> Tested-by: Leo Yan <leo.yan@xxxxxxxxxx>
Thanks!
Applied to the hisilicon arm64 dt tree.
Best Regards,
Wei
> ---
> .../boot/dts/hisilicon/hi6220-coresight.dtsi | 130 ++++++++++++++++--
> 1 file changed, 122 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
> index 651771a73ed6..27f067e87601 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
> @@ -213,7 +213,7 @@
> };
> };
>
> - etm@f659c000 {
> + etm0: etm@f659c000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf659c000 0 0x1000>;
>
> @@ -232,7 +232,7 @@
> };
> };
>
> - etm@f659d000 {
> + etm1: etm@f659d000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf659d000 0 0x1000>;
>
> @@ -251,7 +251,7 @@
> };
> };
>
> - etm@f659e000 {
> + etm2: etm@f659e000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf659e000 0 0x1000>;
>
> @@ -270,7 +270,7 @@
> };
> };
>
> - etm@f659f000 {
> + etm3: etm@f659f000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf659f000 0 0x1000>;
>
> @@ -289,7 +289,7 @@
> };
> };
>
> - etm@f65dc000 {
> + etm4: etm@f65dc000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf65dc000 0 0x1000>;
>
> @@ -308,7 +308,7 @@
> };
> };
>
> - etm@f65dd000 {
> + etm5: etm@f65dd000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf65dd000 0 0x1000>;
>
> @@ -327,7 +327,7 @@
> };
> };
>
> - etm@f65de000 {
> + etm6: etm@f65de000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf65de000 0 0x1000>;
>
> @@ -346,7 +346,7 @@
> };
> };
>
> - etm@f65df000 {
> + etm7: etm@f65df000 {
> compatible = "arm,coresight-etm4x", "arm,primecell";
> reg = <0 0xf65df000 0 0x1000>;
>
> @@ -364,5 +364,119 @@
> };
> };
> };
> +
> + /* System CTIs */
> + /* CTI 0 - TMC and TPIU connections */
> + cti@f6403000 {
> + compatible = "arm,coresight-cti", "arm,primecell";
> + reg = <0 0xf6403000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> + };
> +
> + /* CTI - CPU-0 */
> + cti@f6598000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf6598000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu0>;
> + arm,cs-dev-assoc = <&etm0>;
> + };
> +
> + /* CTI - CPU-1 */
> + cti@f6599000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf6599000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu1>;
> + arm,cs-dev-assoc = <&etm1>;
> + };
> +
> + /* CTI - CPU-2 */
> + cti@f659a000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf659a000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu2>;
> + arm,cs-dev-assoc = <&etm2>;
> + };
> +
> + /* CTI - CPU-3 */
> + cti@f659b000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf659b000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu3>;
> + arm,cs-dev-assoc = <&etm3>;
> + };
> +
> + /* CTI - CPU-4 */
> + cti@f65d8000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf65d8000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu4>;
> + arm,cs-dev-assoc = <&etm4>;
> + };
> +
> + /* CTI - CPU-5 */
> + cti@f65d9000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf65d9000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu5>;
> + arm,cs-dev-assoc = <&etm5>;
> + };
> +
> + /* CTI - CPU-6 */
> + cti@f65da000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf65da000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu6>;
> + arm,cs-dev-assoc = <&etm6>;
> + };
> +
> + /* CTI - CPU-7 */
> + cti@f65db000 {
> + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
> + "arm,primecell";
> + reg = <0 0xf65db000 0 0x1000>;
> +
> + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&cpu7>;
> + arm,cs-dev-assoc = <&etm7>;
> + };
> };
> };
>
