On Fri, 8 May 2020 01:41:13 +0300, Serge Semin wrote: > AXI3-bus is the main communication bus connecting all high-speed > peripheral IP-cores with RAM controller and with MIPS P5600 cores on > Baikal-T1 SoC. This binding describes the DW AMBA 3 AXI Inteconnect > and Errors Handler Block synthesized on top of it, which are > responsible for the AXI-bus traffic arbitration and errors reporting > upstream to CPU. Baikal-T1 AXI-bus DT node is supposed to be compatible > with "be,bt1-axi" and "simple-bus" drivers, should have reg property with > AXI-bus QOS registers space, syscon phandle reference to the Baikal-T1 > System Controller, IRQ line declared, AXI Interconnect reference clock and > reset line. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > Cc: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx> > Cc: Paul Burton <paulburton@xxxxxxxxxx> > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > Cc: Tony Lindgren <tony@xxxxxxxxxxx> > Cc: Tero Kristo <t-kristo@xxxxxx> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > Cc: Jeffrey Hugo <jhugo@xxxxxxxxxxxxxx> > Cc: Linus Walleij <linus.walleij@xxxxxxxxxx> > Cc: Olof Johansson <olof@xxxxxxxxx> > Cc: linux-mips@xxxxxxxxxxxxxxx > Cc: soc@xxxxxxxxxx > > --- > > Rob, I had to remove your Reviewed-by tag, since new changes had been > introduced. > > Changelog v2: > - Move driver to the bus subsystem. > - Use dual GPL/BSD license. > - Use single lined copyright header. > - Lowercase the unit-address. > - Convert a simple EHB block binding to the Baikal-T1 AXI-bus one with > interconnect capabilities support. > - Replace "additionalProperties: false" property with > "unevaluatedProperties: false". > - Add AXI reference clock and reset support. > - Add syscon phandle reference to the Baikal-T1 System Controller node. > --- > .../bindings/bus/baikal,bt1-axi.yaml | 95 +++++++++++++++++++ > 1 file changed, 95 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
