Re: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support

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Hi Lars,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on pinctrl/devel clk/clk-next linus/master v5.7-rc5 next-20200512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-Microchip-Sparx5-SoC/20200514-163536
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=powerpc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/pinctrl/pinctrl-ocelot.c:28: warning: "clrsetbits" redefined
28 | #define clrsetbits(addr, clear, set)          |
In file included from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl/pinctrl-ocelot.c:10:
arch/powerpc/include/asm/io.h:849: note: this is the location of the previous definition
849 | #define clrsetbits(type, addr, clear, set)          |

vim +/clrsetbits +28 drivers/pinctrl/pinctrl-ocelot.c

    27	
  > 28	#define clrsetbits(addr, clear, set) \
    29		writel((readl(addr) & ~(clear)) | (set), (addr))
    30	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip


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