On Wed, May 13, 2020 at 2:13 AM Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> wrote: > > This is the correct fix now but I an afraid not correct before > > commit 3e5ec1db8bfe. > > Sorry, but that's "enable" flag propagation from basic spi_set_cs() to the HW CS > setting callback is a nightmare. In Russia there is a common saying for such > cases, which can be translated as "you can't figure it out without a bottle of > vodka".) > > Actually the fix is correct no matter whether commit 3e5ec1db8bfe is applied or > not. At least I don't see a connection between them. OK that seems to hold given the resoning below so: Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > > What I can't help but asking is: can the native chip select even > > handle active high chip select if not backed by a GPIO? > > Which register would set that polarity? > > No. DW APB SSI doesn't support active-high mode of the native CS's. We had some related discussion what to do with this case when a controller can support active high CS if and only if it is using a GPIO instead of the native CS. We didn't really figure it out, I suppose ideally we should use two flags in the master but that exercise is for another day. Yours. Linus Walleij
