On Tue, 12 May 2020 22:41:46 +0200, Martin Blumenstingl wrote: > This documents the devicetree bindings for the SDHC MMC host controller > found in Meson6, Meson8, Meson8b and Meson8m2 SoCs. It can use a > bus-width of 1/4/8-bit and it supports eMMC spec 4.4x/4.5x including > HS200 mode (up to 100MHz clock). It embeds an internal clock controller > which outputs four clocks (mod_clk, sd_clk, tx_clk and rx_clk) and is > fed by four external input clocks (clkin[0-3]). "pclk" is the module > register clock, it has to be enabled to access the registers. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > --- > .../bindings/mmc/amlogic,meson-mx-sdhc.yaml | 68 +++++++++++++++++++ > 1 file changed, 68 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
