On Fri, May 08, 2020 at 11:22:36AM +0200, Thomas Bogendoerfer wrote:
> On Thu, May 07, 2020 at 10:13:37PM +0300, Serge Semin wrote:
> > On Thu, May 07, 2020 at 01:09:51PM +0200, Thomas Bogendoerfer wrote:
> > > On Wed, May 06, 2020 at 08:42:29PM +0300, Sergey.Semin@xxxxxxxxxxxxxxxxxxxx wrote:
> > > > From: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> > > >
> > > > Indeed according to the P5600/P6000 manual the MAAR pair register
> > > > address field either takes [12:31] bits for 32-bits non-XPA systems
> > > > and [12:35] otherwise. In any case the current address mask is just
> > > > wrong for 64-bit and 32-bits XPA chips. So lets extend it to 39-bits
> > > > value. This shall cover the 64-bits architecture and systems with XPA
> > > > enabled, and won't cause any problem for non-XPA 32-bit systems, since
> > > > the value will be just truncated when written to the 32-bits register.
> > >
> > > according to MIPS32 Priveleged Resoure Architecture Rev. 6.02
> > > ADDR spans from bit 12 to bit 55. So your patch fits only for P5600.
> >
> > > Does the wider mask cause any problems ?
> >
> > No, it won't. Bits written to the [40:62] range will be just ignored,
> > while reading from there should return zeros. Setting GENMASK_ULL(55, 12)
> > would also work. Though this solution is a bit workarounding because
> > MIPS_MAAR_ADDR wouldn't reflect the real mask of the ADDR field. Something
> > like the next macro would work better:
> >
> > +#define MIPS_MAAR_ADDR \
> > +({ \
> > + u64 __mask; \
> > + \
> > + if (cpu_has_lpa && read_c0_pagegrain() & PG_ELPA) { \
> > + __mask = GENMASK_ULL(55, 12); \
> > + else \
> > + __mask = GENMASK_ULL(31, 12); \
> > + \
> > + __mask; \
> > +})
>
> that looks horrible.
>
> > What do you think? What is better: the macro above or setting
> > GENMASK_ULL(55, 12)?
>
> just that one ;-)
Agreed. I'll fix it in v3.
-Sergey
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
