30.04.2020 01:00, Sowjanya Komatineni пишет:
> +/*
> + * VI channel input data type enum.
> + * These data type enum value gets programmed into corresponding Tegra VI
> + * channel register bits.
> + */
> +enum tegra_image_dt {
> + TEGRA_IMAGE_DT_YUV420_8 = 24,
> + TEGRA_IMAGE_DT_YUV420_10,
> +
> + TEGRA_IMAGE_DT_YUV420CSPS_8 = 28,
> + TEGRA_IMAGE_DT_YUV420CSPS_10,
> + TEGRA_IMAGE_DT_YUV422_8,
> + TEGRA_IMAGE_DT_YUV422_10,
> + TEGRA_IMAGE_DT_RGB444,
> + TEGRA_IMAGE_DT_RGB555,
> + TEGRA_IMAGE_DT_RGB565,
> + TEGRA_IMAGE_DT_RGB666,
> + TEGRA_IMAGE_DT_RGB888,
> +
> + TEGRA_IMAGE_DT_RAW6 = 40,
> + TEGRA_IMAGE_DT_RAW7,
> + TEGRA_IMAGE_DT_RAW8,
> + TEGRA_IMAGE_DT_RAW10,
> + TEGRA_IMAGE_DT_RAW12,
> + TEGRA_IMAGE_DT_RAW14,
> +};
Are these format IDs common to all Tegra SoCs or they unique to T210?
