On Fri, May 1, 2020 at 9:29 AM Jim Quinlan <james.quinlan@xxxxxxxxxxxx> wrote: > > From: Jim Quinlan <jquinlan@xxxxxxxxxxxx> > > For various reasons, one may want to disable the ASPM L0s > capability. > > Signed-off-by: Jim Quinlan <jquinlan@xxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > index 77d3e81a437b..084e4cf68b95 100644 > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > @@ -56,6 +56,10 @@ properties: > description: Indicates usage of spread-spectrum clocking. > type: boolean > > + aspm-no-l0s: > + description: Disables ASPM L0s capability. > + type: boolean Copied from rockchip-pcie-host.txt? Let's make this a standard property. It should be documented here[1]. Then this doc just needs 'aspm-no-l0s: true' to indicate you are using it. Rob [1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
