On Thu, 30 Apr 2020 15:50:30 +0800 "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote: > Hi Boris, > > Thank you very much for keep reviewing the patches and more queries... > > On 29/4/2020 11:31 pm, Boris Brezillon wrote: > > On Wed, 29 Apr 2020 23:18:31 +0800 > > "Ramuthevar, Vadivel MuruganX" > > <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote: > > > >> Hi Boris, > >> > >> On 29/4/2020 10:48 pm, Boris Brezillon wrote: > >>> On Wed, 29 Apr 2020 22:33:37 +0800 > >>> "Ramuthevar, Vadivel MuruganX" > >>> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote: > >>> > >>>> Hi Boris, > >>>> > >>>> On 29/4/2020 10:22 pm, Boris Brezillon wrote: > >>>>> On Wed, 29 Apr 2020 18:42:05 +0800 > >>>>> "Ramuthevar, Vadivel MuruganX" > >>>>> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote: > >>>>> > >>>>>> + > >>>>>> +#define EBU_ADDR_SEL(n) (0x20 + (n) * 4) > >>>>>> +#define EBU_ADDR_MASK (5 << 4) > >>>>> > >>>>> It's still unclear what ADDR_MASK is for. Can you add a comment > >>>>> explaining what it does? > >>>> > >>>> Thank you Boris, keep review and giving inputs, will update. > >>> > >>> Can you please explain it here before sending a new version? > >> > >> Memory Region Address Mask: > >> Specifies the number of right-most bits in the base address that should > >> be included in the address comparison. bits positions(7:4). > > > > Okay, then the macro should be > > > > #define EBU_ADDR_MASK(x) ((x) << 4) > > > > And now I'd like you to explain why 5 is the right value for that field > > (I guess that has to do with the position of the CS/ALE/CLE pins). > > 5 : bit 26, 25, 24, 23, 22 to be included for comparison in the That's 6 bits to me, not 5. > ADDR_SELx , it compares only 5 bits. Definitely not what I would qualify as right-most bits. So, you say the comparison always starts at bit 22, and ends at 22+<num-addr-bits>? > >>>> Yes , we are setting both CS0 and CS1 memory access region, if you have > >>>> any concern to optimize, please suggest me, Thanks! > >>> > >>> If you want to setup both CS, and the address written in EBU_ADDR_SEL(x) > >>> is really related to the nand_pa address, then retrieve resources for > >>> all CS ranges. > >> If it's not related, please explain what those > >>> EBU_MEM_BASE_CS_X values encode. > >> > >> Memory Region Base Address > >> FPI Bus addresses are compared to this base address in conjunction with > >> the mask control(EBU_ADDR_MASK). Driver need to program this field! > > > > That's not explaining what the base address should be. Is 'nand_pa' the > > value we should have there? > > The one prorgrammed in the addr_sel register is used by the HW > controller, it remaps to 0x174XX-> CS0 and 0x17CXX->CS1. > The hardware itself, decodes only for 1740xx/17c0xx, other random values > cannot be programmed The question is, is it the same value we have in nand_pa or it is different?
