Xilinx SMPTE UHD-SDI Receiver Subsystem
----------------------------------------
The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create
systems based on SMPTE SDI protocols. It receives unaligned native SDI
streams from the SDI GT PHY and outputs an AXI4-Stream video stream,
native video, or native SDI using Xilinx transceivers as the physical
layer.
SMPTE UHD-SDI Rx Subsystem AXI4-Stream Architecture
+============================================================+
| Native SDI Native Video |
SDI | +=========+ | +============+ | +=============+ |AXI4
Stream | | SMPTE | V | SDI Rx | V | Video In | |Stream
--------->|-->| UHD-SDI |------>| to |----->| to |--->|------->
| | RX | | Native | | AXI4-Stream | |
| +=========+ |Video Bridge| +=============+ |
| | ^ +============+ |
<------|------+ | |
sdi_rx_irq| | |
+=====+===+==================================================+
| ^ ^
| | |
s_axi_aclk sdi_rx_clk video_out_clk
The subsystem consists of the following subcores:
- SMPTE UHD-SDI (RX)
- SDI RX to Video Bridge
- Video In to AXI4-Stream
At design time, this subsystem can be configured in 3Gbps, 6Gbps or
12Gbps mode. It can also be configured to output
- SDI Native stream
- Native Video
- AXI4-Stream
This driver only supports the AXI4-Stream configuration as there is a
corresponding media bus format for YUV 422 10/12 bits per component.
Though the core also supports RBG/YUV444/YUV420 10/12 bits per component,
these are not supported in driver due to lack of corresponding media bus
format currently.
The SDI core has detection modes where in it can be configured to detect
one or more modes from SD (Standard Definition), HD (High Definition),
3GA, 3GB, 6G and 12G modes. When the core has detected the format, it
generates a video lock. In case the source is removed or there is data
corruption, the video may unlock. This is intimated to the application
via a V4L2 event. Other events which application can subscribe are for
overflow and underflow of the video bridges.
The driver gives out the stream properties like width, height, colorformat,
frame interval and progressive/interlaced based on the ST352 packet in SDI
stream. If the ST352 packet is absent, then the values detected by the
SMPTE UHD-SDI Rx core are used.
The SDI core detection modes and detected mode, errors, etc are all
accessible via v4l controls. This driver has been tested with Omnitek
Ultra4K HD, Phabrix Qx and Blackmagic SDI-HDMI convertors.
v2
1/2
- Converted to yaml format
- Removed references to xlnx,video*
- Fixed as per Sakari Ailus and Rob Herring's comments
2/2
- Added DV timing support based on Hans Verkuilś feedback
- More documentation to custom v4l controls and events
- Fixed Hyunś comments
- Added macro for masking and shifting as per Joe Perches comments
- Updated to latest as per Xilinx github repo driver like
adding new DV timings not in mainline yet uptill 03/21/20
Vishal Sagar (2):
media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver
Subsystem
media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver
.../bindings/media/xilinx/xlnx,sdirxss.yaml | 132 +
drivers/media/platform/xilinx/Kconfig | 11 +
drivers/media/platform/xilinx/Makefile | 1 +
.../media/platform/xilinx/xilinx-sdirxss.c | 2162 +++++++++++++++++
include/uapi/linux/xilinx-sdirxss.h | 179 ++
include/uapi/linux/xilinx-v4l2-controls.h | 67 +
6 files changed, 2552 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
create mode 100644 include/uapi/linux/xilinx-sdirxss.h
--
2.21.0
