Re: [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and transfers

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On 4/28/2020 5:52 AM, Hauke Mehrtens wrote:
On 4/24/20 12:42 PM, Dilip Kota wrote:
Synchronize tx, rx and error interrupts by registering to the
same interrupt handler. Interrupt handler will recognize and process
the appropriate interrupt on the basis of interrupt status register.
Also, establish synchronization between the interrupt handler and
transfer operation by taking the locks and registering the interrupt
handler as thread IRQ which avoids the bottom half.
Fixes the wrongly populated interrupt register offsets too.

Fixes: 17f84b793c01 ("spi: lantiq-ssc: add support for Lantiq SSC SPI controller")
Fixes: ad2fca0721d1 ("spi: lantiq-ssc: add LTQ_ prefix to defines")
Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
---
  drivers/spi/spi-lantiq-ssc.c | 89 ++++++++++++++++++++++----------------------
  1 file changed, 45 insertions(+), 44 deletions(-)

Hi,

I tried this patch series on a TP-LINK TD-W8970 (VRX200 with SPI flash)
and the SPI controller is failing like this:
-----
[    6.947194] printk: bootconsole [early0] disabled
[    6.964210] spi-lantiq-ssc 1e100800.spi: Lantiq SSC SPI controller
(Rev 8, TXFS 8, RXFS 8, DMA 1)
[    7.175188] spi-nor spi0.4: SPI transfer timed out
[    7.178558] spi_master spi0: failed to transfer one message from queue
[    7.185120] spi-nor spi0.4: error -145 reading JEDEC ID
[    7.190378] spi-nor: probe of spi0.4 failed with error -2
[    7.199729] libphy: Fixed MDIO Bus: probed
------
It already fails when applying this first patch only.
This change is working successfully on Lightning Mountain SoC.(along with other changes in the patch series, as this alone doesnt configure SPI controller on LGM).

The major changes this patch does is: Finding out the appropriate interrupt by reading the LTQ_SPI_IRNCR register. So i think, this failure could be at interrupt handling. And offsets of LTQ_SPI_IRNICR and LTQ_SPI_IRNCR  registers also corrected. When i added you in the internal review of this patch, i remember you are saying Interrupt controller on VR9/xrx200 is different and acknowledges the interrupts inside the IP  automatically. Does this leads to clearing the interrupt registers LTQ_SPI_IRNCR and LTQ_SPI_IRNICR? If it is the case, the SPI driver cannot figure out the cause of the interrupt and result in timeout.

Could you please print the LTQ_SPI_IRNCR and LTQ_SPI_IRNICR register values in the ISR and share the logs.

Regards,
Dilip



Without this patch is works like this:
-----
[    6.939498] printk: bootconsole [early0] disabled
[    6.954016] spi-lantiq-ssc 1e100800.spi: Lantiq SSC SPI controller
(Rev 8, TXFS 8, RXFS 8, DMA 1)
[    6.975465] spi-nor spi0.4: s25fl064k (8192 Kbytes)
[    6.979066] 4 fixed-partitions partitions found on MTD device spi0.4
[    6.985338] Creating 4 MTD partitions on "spi0.4":
[    6.990127] 0x000000000000-0x000000020000 : "u-boot"
[    6.997422] 0x000000020000-0x0000007c0000 : "firmware"
[    7.212304] random: crng init done
[    8.796128] 2 tplink-fw partitions found on MTD device firmware
[    8.800674] 0x000000020000-0x00000027878f : "kernel"
[    8.807776] 0x000000278790-0x0000007c0000 : "rootfs"
[    8.813611] mtd: device 3 (rootfs) set to be root filesystem
[    8.818268] 1 squashfs-split partitions found on MTD device rootfs
[    8.824123] 0x000000590000-0x0000007c0000 : "rootfs_data"
[    8.831772] 0x0000007c0000-0x0000007d0000 : "config"
[    8.837785] 0x0000007d0000-0x000000800000 : "boardconfig"
[    8.848193] libphy: Fixed MDIO Bus: probed
------

This was done by applying your patches on top of kernel 5.4.35 and
adding this: "spi: lantiq-ssc: Use devm_platform_ioremap_resource() in
lantiq_ssc_probe()" in OpenWrt master.

Hauke



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