Add the DT bindings information for the Digital Blocks DB9000 LCD controller. Also include documentation for the Renesas RZN1 specific compatible string. Signed-off-by: Gareth Williams <gareth.williams.jx@xxxxxxxxxxx> --- .../devicetree/bindings/display/db9000,du.yaml | 87 ++++++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + 2 files changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/db9000,du.yaml diff --git a/Documentation/devicetree/bindings/display/db9000,du.yaml b/Documentation/devicetree/bindings/display/db9000,du.yaml new file mode 100644 index 0000000..73a9311 --- /dev/null +++ b/Documentation/devicetree/bindings/display/db9000,du.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/db9000,du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DB9000 LCD Controller + +maintainers: + - Gareth Williams <gareth.williams.jx@xxxxxxxxxxx> + +description: | + This is an LCD controller by Digital Blocks available for SoCs. The DB9000 + controller reads from the framebuffer to display on a single RGB interface. + Output may be formatted in RGB or BGR. The driver also supports the PWM + logic that is included with the controller. + +properties: + + compatible: + oneOf: + - const: digital-blocks,drm-db9000 + - const: digital-blocks,drm-rzn1 + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: | + A phandle and clock-specifier pair to be used as a pixel clock. + + clock-names: + items: + - const: lcd_eclk + + port: + type: object + description: The panel endpoint connection. + + bits-per-pixel: + description: | + Default is 24. This selects the number of bits used to represent + a single pixel within the controller. + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [8, 16, 24, 32] + + bus-width: + description: | + The width of the interface to the LCD panel. This is needed + if the bits-per-pixel property is set to 16 or less, but the board + connects to a 24-bit panel. In which case, the controller will shift the + 16-bit data to the most significant bits of the device. Default is 24. + + "#pwm-cells": + const: 2 + +required: + - compatible + - "#pwm-cells" + - reg + - interrupts + - clocks + - clock-names + - port + +examples: + - |+ + drm@53004000 { + compatible = "digital-blocks,drm-db9000"; + reg = <0x53004000 0x1000>; + interrupts = <10 97 120>; + clocks = <&sysctrl 26>; + clock-names = "clk_slcd"; + bus-width = <24>; + pinctrl-0 = <&pins_lcd>; + #pwm-cells = <2>; + + port { + drm_point: endpoint@0 { + remote-endpoint = <&display_in>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6992bbb..138f76e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -235,6 +235,8 @@ patternProperties: description: Shenzhen Yagu Electronic Technology Co., Ltd. "^digi,.*": description: Digi International Inc. + "^digital-blocks,.*": + description: Digital Blocks, Inc. "^digilent,.*": description: Diglent, Inc. "^dioo,.*": -- 2.7.4
