Hi Yamada-san, Thank you for your review. 2020年4月20日(月) 20:16 Masahiro Yamada <masahiroy@xxxxxxxxxx>: > > On Mon, Apr 20, 2020 at 7:08 PM Masami Hiramatsu > <masami.hiramatsu@xxxxxxxxxx> wrote: > > > > Add the device tree for Akebi96. Akebi96 is a 96boards certified > > development board based on UniPhir LD20. > > ( https://www.96boards.org/product/akebi96/ ) > > > > This board has; > > - MAX3421 USB-SPI chip on SPI port3 (for USB gadget port) > > - Simple frame buffer with 1080p fixed resolution. > > - I2S port which is connected to aout1b instead of aout1. > > - 3 serial ports, only serial3 has CTS/RTS. > > - No NAND, only eMMC on the board. > > - OP-TEE support. > > > I did not know "OP-TEE support" was board spec. Indeed, that is a feature in the firmware on the board. Actually I was wondering too, but as other boards already have OP-TEE firmware entry, I decided to add it. > > Anyway, I decided to not worry about that. Thanks :) > > > You are adding lots of redundant code. > > Delete as follows. Thanks for the comment. OK, I'll update it. > > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts > b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts > index 84ff98d96751..aaf86162da84 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts > @@ -113,7 +113,6 @@ &serial2 { > &serial3 { > /* LS connector UART0 */ > status = "okay"; > - pinctrl-0 = <&pinctrl_uart3_ctsrts>; > }; > > &spdif_hiecout1 { > @@ -155,11 +154,6 @@ &i2c1 { > status = "okay"; > }; > > -&audio { > - pinctrl-0 = <&pinctrl_aout1b>, > - <&pinctrl_aoutiec1>; > -}; > - > &spi3 { > status = "okay"; > #address-cells = <1>; > @@ -187,14 +181,10 @@ xirq10 { > }; > }; > > -&pinctrl { > - pinctrl_aout1b: aout1b { > - groups = "aout1", "aout1b"; > - function = "aout1"; > - }; > +&pinctrl_aout1 { > + groups = "aout1", "aout1b"; > +}; > > - pinctrl_uart3_ctsrts: uart3-ctsrts { > - groups = "uart3", "uart3_ctsrts"; > - function = "uart3"; > - }; > +&pinctrl_uart3 { > + groups = "uart3", "uart3_ctsrts"; > }; > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > index f93519793bfb..afa90b762ea9 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > @@ -337,7 +337,7 @@ gpio: gpio@55000000 { > <21 217 3>; > }; > > - audio: audio@56000000 { > + audio@56000000 { > compatible = "socionext,uniphier-ld20-aio"; > reg = <0x56000000 0x80000>; > interrupts = <0 144 4>; > > > Lastly, is the pin-setting "aout1", "aout1b" correct ? Yes, according to the schematics of Akebi96(*), it is connected to aout1b(XIRQ*) instead of aout1(AO1*). (*) https://www.96boards.org/documentation/enterprise/akebi96/hardware-docs/akebi96-schematics.pdf Best regards, > > > > -- > Best Regards > Masahiro Yamada -- Masami Hiramatsu
