Hi, first of all: thank you for working on upstreaming this. Especially since you are going to use the new exec_op style in v2 as Boris suggested. > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > > This patch adds the new IP of Nand Flash Controller(NFC) support > on Intel's Lightning Mountain(LGM) SoC. > > DMA is used for burst data transfer operation, also DMA HW supports > aligned 32bit memory address and aligned data access by default. > DMA burst of 8 supported. Data register used to support the read/write > operation from/to device. I am wondering how this new hardware is different from the Lantiq NAND controller IP - for which there is already a driver in mainline (it's in drivers/mtd/nand/raw/xway_nand.c). The CON and WAIT registers look suspiciously similar. As far as I understand the "old" SoCs (VRX200 and earlier) don't have a built-in ECC engine. This seems to have changed with ARX300 though (again, AFAIK). A bit of lineage on these SoCs (initially these were developed by Infineon. Lantiq then started as an Infineon spin-off in 2009 and was then acquired by Intel in 2015): - Danube - ARX100 from 2008/2009 - VRX200 from 2009/2010 - ARX300 from 2014 - GRX350 from 2015/2016 - GRX550 from 2017 - and now finally: LGM from 2020 (est.) The existing xway_nand driver supports the Danube, ARX100 and VRX200 SoCs. Best regards, Martin
