On Mon, Apr 06, 2020 at 03:13:40PM +0200, Dhananjay Kangude wrote: > Add documentation for cadence ddr memory controller EDAC DTS bindings > > Signed-off-by: Dhananjay Kangude <dkangude@xxxxxxxxxxx> > --- > .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 47 ++++++++++++++++++++ > 1 files changed, 47 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml > > diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml > new file mode 100644 > index 0000000..30ea757 > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence DDR IP with ECC support (EDAC) > + > +description: > + This binding describes the Cadence DDR/LPDDR IP with ECC feature enabled > + to detect and correct CE/UE errors. > + > +maintainers: > + - Dhananjay Kangdue <dkangude@xxxxxxxxxxx> > + > +properties: > + compatible: > + enum: > + - cdns,ddr4-mc Surely there's more than 1 version? > + > + reg: > + minItems: 1 > + maxItems: 2 > + items: > + - description: > + Register block of DDR/LPDDR apb registers up to mapped area. > + Mapped area contains the register set for memory controller, > + phy and PI module register set doesn't part of this mapping. doesn't part of this mapping? Need a description for the 2nd region. > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + edac: edac@fd100000 { memory-controller@ > + compatible = "cdns,ddr4-mc-edac"; Doesn't match. > + reg = <0xfd100000 0x4000>; > + interrupts = <0x00 0x01 0x04>; > + }; > +... > -- > 1.7.1 >
