On Thu, Apr 02, 2020 at 01:10:23AM +0300, Laurent Pinchart wrote: > From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xxxxxxxxxx> > > Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed > Processing System Gigabit Transceiver which provides PHY capabilities to > USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. > > Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xxxxxxxxxx> > Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > --- > Changes since v6: > > - Fixed specification of compatible-dependent xlnx,tx-termination-fix > property > - Dropped status property from example > - Use 4 spaces to indent example > > Changes since v5: > > - Document clocks and clock-names properties > - Document resets and reset-names properties > - Replace subnodes with an additional entry in the PHY cells > - Drop lane frequency PHY cell, replaced by reference clock phandle > - Convert bindings to YAML > - Reword the subject line > - Drop Rob's R-b as the bindings have significantly changed > - Drop resets and reset-names properties > --- > .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++ > include/dt-bindings/phy/phy.h | 1 + > 2 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml > > diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml > new file mode 100644 > index 000000000000..d28ddca7b90e > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: GPL-2.0 I think I said this already, but dual license please. Rob
