This patch adds documentation of device tree bindings for the Synopsys HDMI 2.0 TX encoder driver for ARC SoCs. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@xxxxxxxxxxxx> --- .../display/bridge/snps,arc-dw-hdmi.yaml | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/snps,arc-dw-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/snps,arc-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/snps,arc-dw-hdmi.yaml new file mode 100644 index 000000000000..f52fc3b114b0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/snps,arc-dw-hdmi.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/snps,arc-dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI 2.0 TX encoder driver + +maintainers: + - Eugeniy Paltsev <Eugeniy.Paltsev@xxxxxxxxxxxx> + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP + with a companion of Synopsys DesignWare HDMI 2.0 TX PHY IP. + + These DT bindings follow the Synopsys DWC HDMI TX bindings defined in + Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt + with the following device-specific properties. + +properties: + compatible: + const: snps,dw-hdmi-hsdk + + reg: + maxItems: 1 + description: | + Memory mapped base address and length of the DWC HDMI TX registers. + + clocks: + items: + - description: The bus clock for AHB / APB + - description: The internal register configuration clock + + clock-names: + items: + - const: iahb + - const: isfr + + reg-io-width: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 4] + description: + Width of the registers specified by the reg property. The + value is expressed in bytes and must be equal to 1 or 4 if specified. + The register width defaults to 1 if the property is not present. + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Video input endpoints of the controller. + Usually the associated with PGU. + + port@1: + type: object + description: | + Output endpoints of the controller. HDMI connector. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + hdmi: hdmi@0x10000 { + compatible = "snps,dw-hdmi-hsdk"; + reg = <0x10000 0x10000>; + reg-io-width = <4>; + interrupts = <14>; + clocks = <&apbclk>, <&hdmi_pix_clk>; + clock-names = "iahb", "isfr"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_enc_input: endpoint { + remote-endpoint = <&pgu_output>; + }; + }; + + port@1 { + reg = <1>; + hdmi_enc_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-out { + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_enc_out>; + }; + }; + }; + + pgu { + port_o: port { + pgu_output: endpoint { + remote-endpoint = <&hdmi_enc_input>; + }; + }; + }; -- 2.21.1
