This patch adds the new IP of NAND Flash Controller support on Intel's Lightning Mountain(LGM) SoC. DMA is used for burst data transfer operation, also DMA HW supports aligned 32bit memory address and aligned data access by default. DMA burst of 8 supported,Data register used to support the read/write operation from/to device. The NAND controller Subsystem consisting of LGM + ECC-NAND controller supports: NAND Flash Features : -16/8-bit data bus Page + OOB Bytes - 512 + (2 - 13) bytes per page page - 2048 + (7 - 210) bytes per page - 4096 + (13 - 420) bytes per page - 8192 + (26 - 840) bytes per page - Support 32/64/128/256/512/1024/2048/4096/8192/16384/32768 Mbytes flash device - ECC calculation/generation and verification on-the-fly Ramuthevar Vadivel Murugan (2): dt-bindings: mtd: Add YAML for Nand Flash Controller support mtd: rawnand: Add NAND controller support on Intel LGM SoC .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 61 ++ drivers/mtd/nand/raw/Kconfig | 7 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/intel_lgm_nand.c | 678 +++++++++++++++++++++ 4 files changed, 747 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml create mode 100644 drivers/mtd/nand/raw/intel_lgm_nand.c -- 2.11.0
