Some platforms like qualcomms sdm845 SoC have a need to set
a performance state of a power domain for UFS along with
setting the clock rate. Add support for passing this freq/perf state
tuple from DT as an OPP table. Modify the driver to read the OPP
table and register with OPP layer.
Signed-off-by: Rajendra Nayak <rnayak@xxxxxxxxxxxxxx>
Cc: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
Cc: Can Guo <cang@xxxxxxxxxxxxxx>
Cc: Asutosh Das <asutoshd@xxxxxxxxxxxxxx>
Cc: Subhash Jadavani <subhashj@xxxxxxxxxxxxxx>
Cc: linux-scsi@xxxxxxxxxxxxxxx
---
drivers/scsi/ufs/ufshcd.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e04e8b8..172c6fe 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -883,6 +883,16 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
if (ret)
return ret;
+ if (hba->opp_virt_dev) {
+ struct dev_pm_opp *opp;
+ unsigned long freq = scale_up ? INT_MAX : 0;
+ if (scale_up)
+ opp = dev_pm_opp_find_freq_floor(hba->dev, &freq);
+ else
+ opp = dev_pm_opp_find_freq_ceil(hba->dev, &freq);
+ dev_pm_opp_set_rate(hba->dev, dev_pm_opp_get_freq(opp));
+ }
+
list_for_each_entry(clki, head, list) {
if (!IS_ERR_OR_NULL(clki->clk)) {
if (scale_up && clki->max_freq) {
@@ -1339,8 +1349,11 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba)
return 0;
clki = list_first_entry(clk_list, struct ufs_clk_info, list);
- dev_pm_opp_add(hba->dev, clki->min_freq, 0);
- dev_pm_opp_add(hba->dev, clki->max_freq, 0);
+
+ if (dev_pm_opp_of_add_table(hba->dev)) {
+ dev_pm_opp_add(hba->dev, clki->min_freq, 0);
+ dev_pm_opp_add(hba->dev, clki->max_freq, 0);
+ }
ufshcd_vops_config_scaling_param(hba, &ufs_devfreq_profile,
gov_data);
--
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