Hi Tomasz, On Tue, Apr 07, 2020 at 06:46:06PM +0200, Tomasz Figa wrote: > On Tue, Apr 7, 2020 at 6:40 PM Sakari Ailus <sakari.ailus@xxxxxx> wrote: > > > > On Tue, Apr 07, 2020 at 05:47:41PM +0200, Robert Foss wrote: > > > On Tue, 7 Apr 2020 at 14:32, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > > > > > > > Hi Robert, > > > > > > > > On Tue, Apr 07, 2020 at 01:29:05PM +0200, Robert Foss wrote: > > > > > On Tue, 7 Apr 2020 at 10:36, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > > > > > On Mon, Apr 06, 2020 at 11:35:07AM +0300, Sakari Ailus wrote: > > > > > > > > But that 19.2MHz is not a limitation of the device itself, it's a > > > > > > > > limitation of our implementation, so we can instead implement > > > > > > > > something equivalent in Linux using a clk_set_rate to 19.2MHz (to make > > > > > > > > sure that our parent clock is configured at the right rate) and the > > > > > > > > clk_get_rate and compare that to 19.2MHz (to make sure that it's not > > > > > > > > been rounded too far apart from the frequency we expect). > > > > > > > > > > > > > > > > This is doing exactly the same thing, except that we don't encode our > > > > > > > > implementation limitations in the DT, but in the driver instead. > > > > > > > > > > > > > > What I really wanted to say that a driver that doesn't get the clock > > > > > > > frequency from DT but still sets that frequency is broken. > > > > > > > > > > > > > > This frequency is highly system specific, and in many cases only a certain > > > > > > > frequency is usable, for a few reasons: On many SoCs, not all common > > > > > > > frequencies can be used (e.g. 9,6 MHz, 19,2 MHz and 24 MHz; while others > > > > > > > are being used as well), and then that frequency affects the usable CSI-2 > > > > > > > bus frequencies directly --- and of those, only safe, known-good ones > > > > > > > should be used. IOW, getting the external clock frequency wrong typically > > > > > > > has an effect that that none of the known-good CSI-2 bus clock frequencies > > > > > > > are available. > > > > > > > > > > > > So clock-frequency is not about the "Frequency of the xvclk clock in > > > > > > Hertz", but the frequency at which that clock must run on this > > > > > > particular SoC / board to be functional? > > > > > > > > > > > > If so, then yeah, we should definitely keep it, but the documentation > > > > > > of the binding should be made clearer as well. > > > > > > > > > > Alright so, let me summarise the desired approach then. > > > > > > > > There's a separate discussion on the same topic here: > > > > https://lore.kernel.org/linux-media/20200407122106.GD4751@xxxxxxxxxxxxxxxxxxxxxxxxxx/ > > > > > > Thanks for the link. > > > > > > > > > > > > ACPI: > > > > > - Fetch the "clock-frequency" property > > > > > - Verify it to be 19.2Mhz > > > > > > > > > > DT: > > > > > - Fetch the "clock-frequency" property > > > > > - Verify it to be 19.2Mhz > > > > > - Get xvclk clock > > > > > - Get xvclk clock rate > > > > > - Verify xvclk clock rate to be 19.2Mhz > > > > > > > > The current status is that you should > > > > 's/clock-frequency/link-frequencies/', and in order to replace > > > > assigned-clock-rates, you'll want to have a clk_set_rate to 19.2MHz > > > > between steps 3 and 4 > > > > > > Would we want to 's/clock-frequency/link-frequencies/' for ACPI too? > > > I imagine that would cause some breakage. > > > > It would, yes, and it would be no more correct on DT either. > > > > There are basically two possibilities here; either use the clock-frequency > > property and set the frequency, or rely on assigned-clock-rates, and get > > the frequency instead. > > > > The latter, while I understand it is generally preferred, comes with having > > to figure out the register list set that closest matches the frequency > > obtained. The former generally gets around this silently by the clock > > driver setting the closest frequency it can support. > > Wouldn't the former actually cause problems, because the closest > frequency the clock driver can support could be pretty far from the > one requested? (E.g. 19.2 MHz vs 24 MHz) The driver needs to check the > resulting frequency anyway. That's possible, yes; in this case there wouldn't be a guarantee the frequency wouldn't be far off. > > Perhaps a simplified approach of rounding the result of clk_get_rate() > to a multiple of 100 KHz and comparing it to the hardcoded value would > be enough in practice? Then the question is: how much deviation from the expected value is allowed? I think there was another case where such range was checked and because the clock was just slightly more off, the probe failed because of that. I'd in that case check some fairly wide range, and print a warning if the frequency isn't in that range, but still proceed. It's generally impossible to set a precise limit on the tolerance. -- Sakari Ailus
