Hi Maxime, On Tue, Apr 07, 2020 at 02:32:32PM +0200, Maxime Ripard wrote: > Hi Robert, > > On Tue, Apr 07, 2020 at 01:29:05PM +0200, Robert Foss wrote: > > On Tue, 7 Apr 2020 at 10:36, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > > On Mon, Apr 06, 2020 at 11:35:07AM +0300, Sakari Ailus wrote: > > > > > But that 19.2MHz is not a limitation of the device itself, it's a > > > > > limitation of our implementation, so we can instead implement > > > > > something equivalent in Linux using a clk_set_rate to 19.2MHz (to make > > > > > sure that our parent clock is configured at the right rate) and the > > > > > clk_get_rate and compare that to 19.2MHz (to make sure that it's not > > > > > been rounded too far apart from the frequency we expect). > > > > > > > > > > This is doing exactly the same thing, except that we don't encode our > > > > > implementation limitations in the DT, but in the driver instead. > > > > > > > > What I really wanted to say that a driver that doesn't get the clock > > > > frequency from DT but still sets that frequency is broken. > > > > > > > > This frequency is highly system specific, and in many cases only a certain > > > > frequency is usable, for a few reasons: On many SoCs, not all common > > > > frequencies can be used (e.g. 9,6 MHz, 19,2 MHz and 24 MHz; while others > > > > are being used as well), and then that frequency affects the usable CSI-2 > > > > bus frequencies directly --- and of those, only safe, known-good ones > > > > should be used. IOW, getting the external clock frequency wrong typically > > > > has an effect that that none of the known-good CSI-2 bus clock frequencies > > > > are available. > > > > > > So clock-frequency is not about the "Frequency of the xvclk clock in > > > Hertz", but the frequency at which that clock must run on this > > > particular SoC / board to be functional? > > > > > > If so, then yeah, we should definitely keep it, but the documentation > > > of the binding should be made clearer as well. > > > > Alright so, let me summarise the desired approach then. > > There's a separate discussion on the same topic here: > https://lore.kernel.org/linux-media/20200407122106.GD4751@xxxxxxxxxxxxxxxxxxxxxxxxxx/ > > > ACPI: > > - Fetch the "clock-frequency" property > > - Verify it to be 19.2Mhz > > > > DT: > > - Fetch the "clock-frequency" property > > - Verify it to be 19.2Mhz > > - Get xvclk clock > > - Get xvclk clock rate > > - Verify xvclk clock rate to be 19.2Mhz > > The current status is that you should > 's/clock-frequency/link-frequencies/', and in order to replace > assigned-clock-rates, you'll want to have a clk_set_rate to 19.2MHz > between steps 3 and 4 The (CSI-2) link frequency is specified in the endpoint, and is already being read by the V4L2 fwnode framework. -- Sakari Ailus
