On 07. 04. 20, 8:24, Krzysztof Kozlowski wrote:
> On Tue, Apr 07, 2020 at 06:49:29AM +0200, Jiri Slaby wrote:
>> On 07. 04. 20, 1:08, Hyunki Koo wrote:
>>> Support 32-bit access for the TX/RX hold registers UTXH and URXH.
>>>
>>> This is required for some newer SoCs.
>>>
>>> Signed-off-by: Hyunki Koo <hyunki00.koo@xxxxxxxxxxx>
>> ...
>>> ---
>>> drivers/tty/serial/samsung_tty.c | 76 +++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 64 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
>>> index 73f951d65b93..bdf1d4d12cb1 100644
>>> --- a/drivers/tty/serial/samsung_tty.c
>>> +++ b/drivers/tty/serial/samsung_tty.c
>>> @@ -154,12 +154,47 @@ struct s3c24xx_uart_port {
>> ...
>>> -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
>>> +static void wr_reg(struct uart_port *port, u32 reg, u32 val)
>>> +{
>>> + switch (port->iotype) {
>>> + case UPIO_MEM:
>>> + writeb_relaxed(val, portaddr(port, reg));
>>> + break;
>>> + case UPIO_MEM32:
>>> + writel_relaxed(val, portaddr(port, reg));
>>> + break;
>>> + }
>>> +}
>>> +
>>> #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
>>>
>>> +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
>>
>> You need to explain, why you need this _barrier variant now. This change
>> should be done in a separate patch too.
>
> There is no functional change in regard of barrier. The ordered IO was
> used there before.
The patch changes one wr_reg to wr_reg_barrier without any explanation.
This will hardly be accepted.
thanks,
--
js
suse labs
