Add a .yaml schema containing the common properties for the Synopsys DesignWare HDMI TX controller. This isn't a full device tree binding specification, but is meant to be referenced by platform-specific bindings for the IP core. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> --- .../display/bridge/synopsys,dw-hdmi.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml new file mode 100644 index 000000000000..6ebb8f7d2ba8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Synopsys DesignWare HDMI TX Controller + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> + +description: | + This document defines device tree properties for the Synopsys DesignWare HDMI + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree + binding specification by itself but is meant to be referenced by device tree + bindings for the platform-specific integrations of the DWC HDMI TX. + + When referenced from platform device tree bindings the properties defined in + this document are defined as follows. The platform device tree bindings are + responsible for defining whether each property is required or optional. + +properties: + reg: + maxItems: 1 + + reg-io-width: + description: + Width (in bytes) of the registers specified by the reg property. The + register width defaults to 1 if the property is not present. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 4] + + clocks: + minItems: 2 + maxItems: 3 + items: + - description: The bus clock for either AHB and APB + - description: The internal register configuration clock + - description: The HDMI CEC controller main clock + + clock-names: + minItems: 2 + maxItems: 3 + items: + - const: iahb + - const: isfr + - const: cec + + interrupts: + maxItems: 1 + + ports: + type: object + description: | + The connectivity of the DWC HDMI TX with the rest of the system is + expressed using ports as specified in the device graph bindings defined + in Documentation/devicetree/bindings/graph.txt. The numbering of the ports + is platform-specific. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +... -- Regards, Laurent Pinchart
