On Wed, Apr 1, 2020 at 9:35 AM Leonard Crestez <leonard.crestez@xxxxxxx> wrote:
>
> Add nodes for the main interconnect of the imx8m series chips.
>
> These nodes are bound to by devfreq and interconnect drivers.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 24 +++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 24 +++++++++++++++++++++++
> 3 files changed, 72 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 175c28ae10cf..41047b6709b6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -6,10 +6,11 @@
> #include <dt-bindings/clock/imx8mm-clock.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/interconnect/imx8mm.h>
>
> #include "imx8mm-pinfunc.h"
>
> / {
> interrupt-parent = <&gic>;
> @@ -860,10 +861,33 @@
> status = "disabled";
> };
>
> };
>
> + noc: interconnect@32700000 {
> + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
> + reg = <0x32700000 0x100000>;
> + clocks = <&clk IMX8MM_CLK_NOC>;
> + fsl,ddrc = <&ddrc>;
> + #interconnect-cells = <1>;
> + operating-points-v2 = <&noc_opp_table>;
> +
> + noc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-150M {
> + opp-hz = /bits/ 64 <150000000>;
> + };
> + opp-375M {
> + opp-hz = /bits/ 64 <375000000>;
> + };
> + opp-750M {
> + opp-hz = /bits/ 64 <750000000>;
Out of curiosity, the 8M Mini runs up to 750M, and the 8M Nano and
8MQ run up to 800. The 8MQ had a patch to increase the assigned clock
speed for the NOC to 800MHz
See: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/patch/arch/arm64/boot/dts/freescale?id=912b9dacf3f0ffad55e1a1b3c5af0e433ebdb5dd)
The 8M Mini and 8M Nano appear to be setting the default speed to 0.
Should the 8M Mini or 8M Nano do something similar to what the 8MQ
did, or does this series negate the need for such a patch?
thanks
adam
> + };
> + };
> + };
> +
> aips4: bus@32c00000 {
> compatible = "fsl,aips-bus", "simple-bus";
> reg = <0x32df0000 0x10000>;
> #address-cells = <1>;
> #size-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 88e7d74e077f..e8a55956813f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -6,10 +6,11 @@
> #include <dt-bindings/clock/imx8mn-clock.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/interconnect/imx8mn.h>
>
> #include "imx8mn-pinfunc.h"
>
> / {
> interrupt-parent = <&gic>;
> @@ -751,10 +752,33 @@
> status = "disabled";
> };
>
> };
>
> + noc: interconnect@32700000 {
> + compatible = "fsl,imx8mn-noc", "fsl,imx8m-noc";
> + reg = <0x32700000 0x100000>;
> + clocks = <&clk IMX8MN_CLK_NOC>;
> + fsl,ddrc = <&ddrc>;
> + #interconnect-cells = <1>;
> + operating-points-v2 = <&noc_opp_table>;
> +
> + noc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + opp-600M {
> + opp-hz = /bits/ 64 <600000000>;
> + };
> + opp-800M {
> + opp-hz = /bits/ 64 <800000000>;
> + };
> + };
> + };
> +
> aips4: bus@32c00000 {
> compatible = "fsl,aips-bus", "simple-bus";
> reg = <0x32df0000 0x10000>;
> #address-cells = <1>;
> #size-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index ea93bc4b7d7e..3a208feec74c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -9,10 +9,11 @@
> #include <dt-bindings/reset/imx8mq-reset.h>
> #include <dt-bindings/gpio/gpio.h>
> #include "dt-bindings/input/input.h"
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/interconnect/imx8mq.h>
> #include "imx8mq-pinfunc.h"
>
> / {
> interrupt-parent = <&gpc>;
>
> @@ -1026,10 +1027,33 @@
> fsl,num-rx-queues = <3>;
> status = "disabled";
> };
> };
>
> + noc: interconnect@32700000 {
> + compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
> + reg = <0x32700000 0x100000>;
> + clocks = <&clk IMX8MQ_CLK_NOC>;
> + fsl,ddrc = <&ddrc>;
> + #interconnect-cells = <1>;
> + operating-points-v2 = <&noc_opp_table>;
> +
> + noc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-133M {
> + opp-hz = /bits/ 64 <133333333>;
> + };
> + opp-400M {
> + opp-hz = /bits/ 64 <400000000>;
> + };
> + opp-800M {
> + opp-hz = /bits/ 64 <800000000>;
> + };
> + };
> + };
> +
> bus@32c00000 { /* AIPS4 */
> compatible = "fsl,aips-bus", "simple-bus";
> reg = <0x32df0000 0x10000>;
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.17.1
>
>
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