Add a documentation for the Rockchip Camera Interface controller binding. This controller can be found on platforms such as the PX30 or the RK3288, the PX30 being the only platform supported so far. Signed-off-by: Maxime Chevallier <maxime.chevallier@xxxxxxxxxxx> --- .../bindings/media/rockchip-cif.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-cif.yaml diff --git a/Documentation/devicetree/bindings/media/rockchip-cif.yaml b/Documentation/devicetree/bindings/media/rockchip-cif.yaml new file mode 100644 index 000000000000..87fb5e136edd --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-cif.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip-cif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Camera Interface (CIF) + +maintainers: + - Maxime Chevallier <maxime.chevallier@xxxxxxxxxxx> + +description: |- +Camera Interface for Rockcip platforms + +properties: + compatible: + const: rockchip,px30-cif + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + - description: CIF_OUT + + clock-names: + items: + - const: aclk_cif + - const: hclk_cif + - const: pclk_cif + - const: cif_out + + resets: + items: + - description: Reset CIF A + - description: Reset CIF H + - description: Reset CIF PCLK IN + + reset-names: + items: + - const: rst_cif_a + - const: rst_cif_h + - const: rst_cif_pclkin + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + # See ./video-interfaces.txt for details + port: + type: object + additionalProperties: false + + properties: + endpoint: + type: object + + properties: + remote-endpoint: true + + required: + - remote-endpoint + + required: + - endpoint + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + cif: cif@ff490000 { + compatible = "rockchip,px30-cif"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; + clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; + power-domains = <&power PX30_PD_VI>; + port { + cif_in: endpoint { + remote-endpoint = <&tw9900_out>; + }; + }; + }; +... -- 2.24.1
