On Fri, Apr 3, 2020 at 5:41 PM Anson Huang <Anson.Huang@xxxxxxx> wrote:
>
> i.MX8MP has a TMU inside which supports two thermal zones, add support
> for them.
>
> Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx>
Reviewed-by: Amit Kucheria <amit.kucheria@xxxxxxxxxx>
> ---
> Changes since V3:
> - Drop some '0x' prefix;
> - Add cpufreq cooling for soc thermal zone as well to fit the passive trip point.
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 74 +++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 9b1616e..77aff14 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
>
> #include "imx8mp-pinfunc.h"
>
> @@ -43,6 +44,7 @@
> clocks = <&clk IMX8MP_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_1: cpu@1 {
> @@ -53,6 +55,7 @@
> clocks = <&clk IMX8MP_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_2: cpu@2 {
> @@ -63,6 +66,7 @@
> clocks = <&clk IMX8MP_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_3: cpu@3 {
> @@ -73,6 +77,7 @@
> clocks = <&clk IMX8MP_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_L2: l2-cache0 {
> @@ -127,6 +132,68 @@
> method = "smc";
> };
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 0>;
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device =
> + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + soc-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 1>;
> + trips {
> + soc_alert0: trip0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + soc_crit0: trip1 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&soc_alert0>;
> + cooling-device =
> + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -215,6 +282,13 @@
> gpio-ranges = <&iomuxc 0 114 30>;
> };
>
> + tmu: tmu@30260000 {
> + compatible = "fsl,imx8mp-tmu";
> + reg = <0x30260000 0x10000>;
> + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> wdog1: watchdog@30280000 {
> compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
> reg = <0x30280000 0x10000>;
> --
> 2.7.4
>
