On Tue, Mar 31, 2020 at 09:08:12AM +0530, Kishon Vijay Abraham I wrote: > Hi Rob, > > On 3/30/2020 9:31 PM, Rob Herring wrote: > > On Fri, Mar 27, 2020 at 04:17:25PM +0530, Kishon Vijay Abraham I wrote: > >> Deprecate cdns,max-outbound-regions and cdns,no-bar-match-nbits for > >> host mode as both these could be derived from "ranges" and "dma-ranges" > >> property. "cdns,max-outbound-regions" property would still be required > >> for EP mode. > >> > >> Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx> > >> --- > >> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 2 +- > >> .../bindings/pci/cdns,cdns-pcie-host.yaml | 3 +-- > >> .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 25 +++++++++++++++++++ > >> .../bindings/pci/cdns-pcie-host.yaml | 10 ++++++++ > >> .../devicetree/bindings/pci/cdns-pcie.yaml | 8 ------ > >> 5 files changed, 37 insertions(+), 11 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > >> index 2996f8d4777c..50ce5d79d2c7 100644 > >> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > >> @@ -10,7 +10,7 @@ maintainers: > >> - Tom Joseph <tjoseph@xxxxxxxxxxx> > >> > >> allOf: > >> - - $ref: "cdns-pcie.yaml#" > >> + - $ref: "cdns-pcie-ep.yaml#" > >> - $ref: "pci-ep.yaml#" > >> > >> properties: > >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> index cabbe46ff578..84a8f095d031 100644 > >> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> @@ -45,8 +45,6 @@ examples: > >> #size-cells = <2>; > >> bus-range = <0x0 0xff>; > >> linux,pci-domain = <0>; > >> - cdns,max-outbound-regions = <16>; > >> - cdns,no-bar-match-nbits = <32>; > >> vendor-id = <0x17cd>; > >> device-id = <0x0200>; > >> > >> @@ -57,6 +55,7 @@ examples: > >> > >> ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, > >> <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; > >> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; > >> > >> #interrupt-cells = <0x1>; > >> > >> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml > >> new file mode 100644 > >> index 000000000000..6150a7a7bdbf > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml > >> @@ -0,0 +1,25 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"; > >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > >> + > >> +title: Cadence PCIe Device > >> + > >> +maintainers: > >> + - Tom Joseph <tjoseph@xxxxxxxxxxx> > >> + > >> +allOf: > >> + - $ref: "cdns-pcie.yaml#" > >> + > >> +properties: > >> + cdns,max-outbound-regions: > >> + description: maximum number of outbound regions > >> + allOf: > >> + - $ref: /schemas/types.yaml#/definitions/uint32 > >> + minimum: 1 > >> + maximum: 32 > >> + default: 32 > > > > I have a feeling that as the PCI endpoint binding evolves this won't be > > necessary. I can see a common need to define the number of BARs for an > > endpoint and then this will again just be error checking. > > For every buffer given by the host, we have to create a new outbound > translation. If there are no outbound regions, we have to report the error to > the endpoint function driver. At-least for reporting the error, we'd need to > have this binding no? But isn't the endpoint defined to have some number of BARs? The PCI host doesn't decide that. > > > > What's the result if you write to a non-existent region in register > > CDNS_PCIE_AT_OB_REGION_PCI_ADDR0/1? If the register is non-existent and > > doesn't abort, you could detect this instead. > > I'm not sure if we should ever try to write to a non-existent register though > the behavior could be different in different platforms. IMHO maximum number of > outbound regions is a HW property and is best described in device tree. AIUI, PCI defines non-existent (config space) registers to return all 1s. Not sure if this register is in PCI config space or the host SoC bus (e.g. AXI). It seems PCI bridges get done both ways from what I've seen. Rob
