On Fri, 20 Mar 2020 14:45:24 +0100, Linus Walleij wrote: > This adds YAML device tree bindings for the Integrator/AP > logic modules. These are plug-in tiles used typically for > FPGA prototyping. > > Cc: devicetree@xxxxxxxxxxxxxxx > Cc: Robin Murphy <robin.murphy@xxxxxxx> > Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > --- > ChangeLog v2->v3: > - Put proper ranges around the addresses managed by the > LM bus, 0xc0000000-0xffffffff as > <0xc0000000 0xc0000000 0x40000000> > - Put unit name on the first LM bus bus@c0000000 in the > example in the bindings. > - Drop leading zeroes in the unit names of the devices > in the example. > ChangeLog v1->v2: > - Fix Logical->Logic spelling error > - Set generic names for bus and serial > - Just map the addresses 1:1 and use empty ranges, as the > LM's don't really translate the address. > - Provide proper DMA ranges: the LM modules see the RAM at > the system-wide alias @80000000 rather than 1:1. > - Drop the reg from the bus node (we just need the ranges) > - Make the regexp for the bus node such that @address is > optional, as we don't require any reg on the node > --- > .../bindings/bus/arm,integrator-ap-lm.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/arm,integrator-ap-lm.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
