On 05/15/2014 01:30 PM, Bart Tanghe wrote:
>
>
> On 05/15/2014 12:33 PM, Michal Simek wrote:
>> On 05/15/2014 10:50 AM, Bart Tanghe wrote:
>>> On 05/15/2014 09:23 AM, Arnd Bergmann wrote:
>>>> On Wednesday 14 May 2014 13:26:13 Bart Tanghe wrote:
>>>>> @@ -0,0 +1,20 @@
>>>>> +Xilinx PWM controller
>>>>> +
>>>>> +Required properties:
>>>>> +- compatible: should be "xlnx,pwm-xlnx"
>>>>> +- add a clock source to the description
>>>>> +
>>>>> +Examples:
>>>>> +
>>>>> + axi_timer_0: timer@42800000 {
>>>>> + clock-frequency = <100000000>;
>>>>> + clocks = <&clkc 15>;
>>>>> + compatible = "xlnx,xlnx-pwm";
>>>>> + reg = <0x42800000 0x10000>;
>>>>> + xlnx,count-width = <0x20>;
>>>>> + xlnx,gen0-assert = <0x1>;
>>>>> + xlnx,gen1-assert = <0x1>;
>>>>> + xlnx,one-timer-only = <0x0>;
>>>>> + xlnx,trig0-assert = <0x1>;
>>>>> + xlnx,trig1-assert = <0x1>;
>>>>> + } ;
>>>>>
>>>>
>>>> It seems you are missing a mandatory "#pwm-cells" property.
>>>> How is anybody supposed to use this?
>>>>
>>>> Arnd
>>>>
>>>
>>> I've added some additional information in the documentation
>>>
>>>
>>>
>>> Xilinx PWM controller
>>>
>>> This driver works together with the Xilinx Axi timer hardware core.
>>> The core is available for the microblaze, powerpc and arm based Xilinx
>>> platforms.
>>>
>>> The axi timer core is implemented in the pl (programmable logic) of the
>>> fpga. The amount is user defined. Each core has two timers and one pwm output.
>>
>> For PWM you have to have 2 timers but core itself can be configured
>> to any configuration and I expect that any output has to be used.
>>
>> Can you describe me your testing enviroment with zedboard?
>> Do you use any additional hw or are using just leds or any device
>> on zedboard?
>>
>> Thanks,
>> Michal
>>
>>
>
> I'm using the 2 internal timers of the axi_timer core. I've attached the pwm output of the timer core to one of the leds. The generate out0 and generate out1 signals aren't attached.
> I've added 4 axi timers to the design, so I can use the 4 leds of zedboard to visualize and measure the pwm signal.
ok, that's configuration what I expected.
Can you add or just send me this hw design? I can create it myself but
no reason to spend time on it when you have it.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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