Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu <roger.lu@xxxxxxxxxxxx>
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.../devicetree/bindings/power/mtk-svs.txt | 76 +++++++++++++++++++
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+* Mediatek Smart Voltage Scaling (MTK SVS)
+
+This describes the device tree binding for the MTK SVS controller (bank)
+which helps provide the optimized CPU/GPU/CCI voltages. This device also
+needs thermal data to calculate thermal slope for accurately compensate
+the voltages when temperature change.
+
+Required properties:
+- compatible:
+ - "mediatek,mt8183-svs" : For MT8183 family of SoCs
+- reg: Address range of the MTK SVS controller.
+- interrupts: IRQ for the MTK SVS controller.
+- clocks, clock-names: Clocks needed for the svs hardware. required
+ clocks are:
+ "main": Main clock for svs controller to work.
+- nvmem-cells: Phandle to the calibration data provided by a nvmem device.
+- nvmem-cell-names: Should be "svs-calibration-data" and "calibration-data"
+
+Subnodes:
+- svs-cpu-little: SVS bank device node of little CPU
+ compatible: "mediatek,mt8183-svs-cpu-little"
+ operating-points-v2: OPP table hooked by SVS little CPU bank.
+ SVS will optimze this OPP table voltage part.
+ vcpu-little-supply: PMIC buck of little CPU
+- svs-cpu-big: SVS bank device node of big CPU
+ compatible: "mediatek,mt8183-svs-cpu-big"
+ operating-points-v2: OPP table hooked by SVS big CPU bank.
+ SVS will optimze this OPP table voltage part.
+ vcpu-big-supply: PMIC buck of big CPU
+- svs-cci: SVS bank device node of CCI
+ compatible: "mediatek,mt8183-svs-cci"
+ operating-points-v2: OPP table hooked by SVS CCI bank.
+ SVS will optimze this OPP table voltage part.
+ vcci-supply: PMIC buck of CCI
+- svs-gpu: SVS bank device node of GPU
+ compatible: "mediatek,mt8183-svs-gpu"
+ operating-points-v2: OPP table hooked by SVS GPU bank.
+ SVS will optimze this OPP table voltage part.
+ vgpu-supply: PMIC buck of GPU
+
+Example:
+
+ svs: svs@1100b000 {
+ compatible = "mediatek,mt8183-svs";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main_clk";
+ nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
+ nvmem-cell-names = "svs-calibration-data", "calibration-data";
+
+ svs_cpu_little: svs-cpu-little {
+ compatible = "mediatek,mt8183-svs-cpu-little";
+ operating-points-v2 = <&cluster0_opp>;
+ vcpu-little-supply = <&mt6358_vproc12_reg>;
+ };
+
+ svs_cpu_big: svs-cpu-big {
+ compatible = "mediatek,mt8183-svs-cpu-big";
+ operating-points-v2 = <&cluster1_opp>;
+ vcpu-big-supply = <&mt6358_vproc11_reg>;
+ };
+
+ svs_cci: svs-cci {
+ compatible = "mediatek,mt8183-svs-cci";
+ operating-points-v2 = <&cci_opp>;
+ vcci-supply = <&mt6358_vproc12_reg>;
+ };
+
+ svs_gpu: svs-gpu {
+ compatible = "mediatek,mt8183-svs-gpu";
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
+ operating-points-v2 = <&gpu_opp_table>;
+ vgpu-spply = <&mt6358_vgpu_reg>;
+ };
+ };
--
2.18.0
