On Sat, 2020-03-07 at 11:56 -0800, Moritz Fischer wrote: > [External] > > On Sat, Mar 07, 2020 at 02:26:04PM +0000, Jonathan Cameron wrote: > > On Fri, 6 Mar 2020 13:00:54 +0200 > > Alexandru Ardelean <alexandru.ardelean@xxxxxxxxxx> wrote: > > > > > The format for all ADI AXI IP cores is the same. > > > i.e. 'major.minor.patch'. > > > > > > This patch adds the helper macros to be re-used in ADI AXI drivers. > > > > > > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@xxxxxxxxxx> > Acked-by: Moritz Fischer <mdf@xxxxxxxxxx> > > > Again, trivial but needs a Moritz ack as it's his subsystem. > > I had originally asked to not put it under include/linux/fpga, but alas, > now it's here :) > > It never made much sense imho to drop it under linux/fpga just because > it's a hardware implemented in an FPGA.... We can always move it. I don't remember about any discussion on this matter. Or maybe I wasn't included. Or maybe I have some severe case of amnesia or carelessness for omitting threads. I am terrible at following threads. Apologies for anything on my part. If you propose another location, I can spin-up a patch on it. These reg-definitions are common to all ADI HDL regs. Maybe more may come up as stuff gets upstreamed. The full-blown/internal version we have is: https://github.com/analogdevicesinc/linux/blob/master/include/linux/fpga/adi-axi-common.h It tries to define some things that are common between Intel, Xilinx and ADI IP cores across [these and hopefully other] FPGA boards. I'm not saying it's doing a good job of that at the moment. ¯\_(ツ)_/¯ Thanks Alex > > Cheers, > Moritz
