On Tue, May 13, 2014 at 11:10:38AM +0100, Thomas Petazzoni wrote: > --- a/Documentation/devicetree/bindings/arm/l2cc.txt > +++ b/Documentation/devicetree/bindings/arm/l2cc.txt > @@ -8,6 +8,8 @@ Required properties: > > - compatible : should be one of: > "arm,pl310-cache" > + "arm,pl310-coherent-cache", used for I/O coherent platforms using > + the PL310 cache > "arm,l220-cache" > "arm,l210-cache" > "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" The binding name kind of implies that we have a transparent PL310 cache (at least to me), which is not the case. I would rather have a specific dma-coherent property or something similar since it's not another type of PL310 but rather a different SoC topology. But I recall you mentioned that you can't make this decision at the DT level since you don't know before whether the SoC is I/O coherent or not. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
