Hi On Sat, Feb 29, 2020 at 05:07:43PM +0100, Kevin Hilman wrote: > Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> writes: > > > On Fri, Jan 24, 2020 at 12:29:36AM +0100, Remi Pommarel wrote: > >> PCIe device probing failures have been seen on AXG platforms and were > >> due to unreliable clock signal output. Setting HHI_MIPI_CNTL0[26] bit > >> in MIPI's PHY registers solved the problem. This bit controls band gap > >> reference. > >> > >> As discussed here [1] one of these shared MIPI/PCIE analog PHY register > >> bits was implemented in the clock driver as CLKID_MIPI_ENABLE. This adds > >> a PHY driver to control this bit instead, as well as setting the band > >> gap one in order to get reliable PCIE communication. > >> > >> While at it add another PHY driver to control PCIE only PHY registers, > >> making AXG code more similar to G12A platform thus allowing to remove > >> some specific platform handling in pci-meson driver. > >> > >> Please note that CLKID_MIPI_ENABLE removable will be done in a different > >> serie. > >> > >> Changes since v5: > >> - Add additionalProperties in device tree binding documentation > >> - Make analog PHY required > >> > >> Changes since v4: > >> - Rename the shared MIPI/PCIe PHY to analog > >> - Chain the MIPI/PCIe PHY to the PCIe one > >> > >> Changes since v3: > >> - Go back to the shared MIPI/PCIe phy driver solution from v2 > >> - Remove syscon usage > >> - Add all dt-bindings documentation > >> > >> Changes since v2: > >> - Remove shared MIPI/PCIE device driver and use syscon to access register > >> in PCIE only driver instead > >> - Include devicetree documentation > >> > >> Changes sinve v1: > >> - Move HHI_MIPI_CNTL0 bit control in its own PHY driver > >> - Add a PHY driver for PCIE_PHY registers > >> - Modify pci-meson.c to make use of both PHYs and remove specific > >> handling for AXG and G12A > >> > >> [1] https://lkml.org/lkml/2019/12/16/119 > >> > >> Remi Pommarel (7): > >> dt-bindings: Add AXG PCIE PHY bindings > >> dt-bindings: Add AXG shared MIPI/PCIE analog PHY bindings > >> dt-bindings: PCI: meson: Update PCIE bindings documentation > >> arm64: dts: meson-axg: Add PCIE PHY nodes > >> phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver > >> phy: amlogic: Add Amlogic AXG PCIE PHY Driver > >> PCI: amlogic: Use AXG PCIE > >> > >> .../bindings/pci/amlogic,meson-pcie.txt | 22 +- > >> .../amlogic,meson-axg-mipi-pcie-analog.yaml | 35 ++++ > >> .../bindings/phy/amlogic,meson-axg-pcie.yaml | 52 +++++ > >> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 16 ++ > >> drivers/pci/controller/dwc/pci-meson.c | 116 ++--------- > >> drivers/phy/amlogic/Kconfig | 22 ++ > >> drivers/phy/amlogic/Makefile | 12 +- > >> .../amlogic/phy-meson-axg-mipi-pcie-analog.c | 188 +++++++++++++++++ > >> drivers/phy/amlogic/phy-meson-axg-pcie.c | 192 ++++++++++++++++++ > >> 9 files changed, 543 insertions(+), 112 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml > >> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml > >> create mode 100644 drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c > >> create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c > > > > Hi Remi, > > > > I am ready to pull this series in, do you want me to ? Or you prefer > > it to go via a different tree upstream ? > > To avoid conflicts, I'll take the DT patch (PATCH 4/7) through my > amlogic tree, but feel free to take the rest. Hi Lorenzo, Kevin, The only issue I see here is that PATCH 6/7 does not have any Reviewed-by/Acked-by, but if that is ok with you that will be nice to have this upstream, thanks. Sorry for the mail delivery error you could have received, silly me forgot to renew the domain name. Thanks Remi
