Add documentation for cadence ddr memory controller EDAC DTS bindings Signed-off-by: Dhananjay Kangude <dkangude@xxxxxxxxxxx> --- .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml new file mode 100644 index 000000000000..d83d8840d57b --- /dev/null +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DDR IP with ECC support (EDAC) + +description: + This binding describes the Cadence DDR/LPDDR IP with ECC feature enabled + to detect and correct CE/UE errors. + +maintainers: + - Dhananjay Kangdue <dkangude@xxxxxxxxxxx> + +properties: + compatible: + enum: + - cdns,cadence-ddr4-mc-edac + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + + reg: + minItems: 1 + maxItems: 2 + items: + - description: + Register block of DDR/LPDDR apb registers up to mapped area. + Mapped area contains the register set for memory controller, + phy and PI module register set doesn't part of this mapping. + + interrupts: + maxItems: 1 + +required: + - compatible + - ranges + - reg + - interrupts + +additionalProperties: false + +examples: + - | + edac: edac@fd100000 { + compatible = "cdns,cadence-ddr4-mc-edac"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd100000 0x4000>; + interrupts = <0x00 0x01 0x04>; + }; +... -- 2.15.0
