On Wed, Feb 26, 2020 at 06:08:56PM +0000, Andre Przywara wrote:
> Convert the Calxeda ComboPHY binding to DT schema format using
> json-schema.
> There is no driver in the Linux kernel matching the compatible
> string, but the nodes are parsed by the SATA driver, which links to them
> using its port-phys property.
>
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> ---
> .../bindings/phy/calxeda-combophy.txt | 17 -------
> .../bindings/phy/calxeda-combophy.yaml | 47 +++++++++++++++++++
> 2 files changed, 47 insertions(+), 17 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.txt
> create mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt b/Documentation/devicetree/bindings/phy/calxeda-combophy.txt
> deleted file mode 100644
> index 6622bdb2e8bc..000000000000
> --- a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -Calxeda Highbank Combination Phys for SATA
> -
> -Properties:
> -- compatible : Should be "calxeda,hb-combophy"
> -- #phy-cells: Should be 1.
> -- reg : Address and size for Combination Phy registers.
> -- phydev: device ID for programming the combophy.
> -
> -Example:
> -
> - combophy5: combo-phy@fff5d000 {
> - compatible = "calxeda,hb-combophy";
> - #phy-cells = <1>;
> - reg = <0xfff5d000 0x1000>;
> - phydev = <31>;
> - };
> -
> diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
> new file mode 100644
> index 000000000000..2ef68b95fae1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Calxeda Highbank Combination PHYs binding for SATA
> +
> +description: |
> + The Calxeda Combination PHYs connect the SoC to the internal fabric
> + and to SATA connectors. The PHYs support multiple protocols (SATA,
> + SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
> + controller).
> + Programming the PHYs is typically handled by those device drivers,
> + not by a dedicated PHY driver.
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@xxxxxxx>
> +
> +properties:
> + compatible:
> + const: calxeda,hb-combophy
> +
> + '#phy-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + phydev:
> + description: device ID for programming the combophy.
> + $ref: /schemas/types.yaml#/definitions/uint32
I guess you can limit the range here, or does it cover the whole u32
range?
Maxime
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