On Wed, Feb 26, 2020 at 06:08:53PM +0000, Andre Przywara wrote: > Convert the Calxeda clock bindings to DT schema format using json-schema. > > This just covers the actual PLL and divider clock nodes. In the actual > DTs they are somewhat unconnected (no ranges or bus compatible) children > of the sregs node, but for the actual clock bindings this is not > relevant. > > One oddity is that the addresses are relative to the parent node, > without that being pronounced using a ranges property. > But this is too late to fix now. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > Cc: Michael Turquette <mturquette@xxxxxxxxxxxx> > Cc: Stephen Boyd <sboyd@xxxxxxxxxx> > Cc: linux-clk@xxxxxxxxxxxxxxx > > --- > .../devicetree/bindings/clock/calxeda.txt | 17 ---- > .../devicetree/bindings/clock/calxeda.yaml | 83 +++++++++++++++++++ > 2 files changed, 83 insertions(+), 17 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/clock/calxeda.txt > create mode 100644 Documentation/devicetree/bindings/clock/calxeda.yaml > > diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt > deleted file mode 100644 > index 0a6ac1bdcda1..000000000000 > --- a/Documentation/devicetree/bindings/clock/calxeda.txt > +++ /dev/null > @@ -1,17 +0,0 @@ > -Device Tree Clock bindings for Calxeda highbank platform > - > -This binding uses the common clock binding[1]. > - > -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > - > -Required properties: > -- compatible : shall be one of the following: > - "calxeda,hb-pll-clock" - for a PLL clock > - "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the > - A9 clock. > - "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. > - "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. > -- reg : shall be the control register offset from SYSREGs base for the clock. > -- clocks : shall be the input parent clock phandle for the clock. This is > - either an oscillator or a pll output. > -- #clock-cells : from common clock binding; shall be set to 0. > diff --git a/Documentation/devicetree/bindings/clock/calxeda.yaml b/Documentation/devicetree/bindings/clock/calxeda.yaml > new file mode 100644 > index 000000000000..0ad66af0eb0c > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/calxeda.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/calxeda.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Device Tree Clock bindings for Calxeda highbank platform > + > +description: | > + This binding covers the Calxeda SoC internal peripheral and bus clocks > + as used by peripherals. The clocks live inside the "system register" > + region of the SoC, so are typically presented as children of an > + "hb-sregs" node. > + > +maintainers: > + - Andre Przywara <andre.przywara@xxxxxxx> > + > +properties: > + "#clock-cells": > + const: 0 > + > + compatible: > + enum: > + - calxeda,hb-pll-clock > + - calxeda,hb-a9periph-clock > + - calxeda,hb-a9bus-clock > + - calxeda,hb-emmc-clock > + > + reg: > + maxItems: 1 > + > + clocks: > + $ref: /schemas/types.yaml#/definitions/phandle-array There's no need to specify the type, it's already checked by a schemas there: https://github.com/devicetree-org/dt-schema/blob/master/schemas/clock/clock.yaml Maxime
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