On Fri, Feb 21, 2020 at 02:39:14PM +0800, sherry sun wrote: > From: Sherry Sun <sherry.sun@xxxxxxx> > > Add documentation for i.MX8MP DDRC binding based on synopsys_edac doc, > which use the same memory-controller IP. > > Signed-off-by: Sherry Sun <sherry.sun@xxxxxxx> > --- > .../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > index 9d32762c47e1..5c03959a451f 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > @@ -6,16 +6,20 @@ bus width configurations. > The Zynq DDR ECC controller has an optional ECC support in half-bus width > (16-bit) configuration. > > -These both ECC controllers correct single bit ECC errors and detect double bit > +The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width > +configurations. > + > +These all ECC controllers correct single bit ECC errors and detect double bit All the ECC... With that, Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > ECC errors. > > Required properties: > - compatible: One of: > - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller > - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller > + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller > - reg: Should contain DDR controller registers location and length. > > -Required properties for "xlnx,zynqmp-ddrc-2.40a": > +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": > - interrupts: Property with a value describing the interrupt number. > > Example: > -- > 2.17.1 >
