> -----Original Message-----
> From: Peng Fan <peng.fan@xxxxxxx>
> Sent: Tuesday, February 25, 2020 3:49 PM
> To: sboyd@xxxxxxxxxx; shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx;
> festevam@xxxxxxxxx; Abel Vesa <abel.vesa@xxxxxxx>
> Cc: kernel@xxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>; Anson Huang
> <anson.huang@xxxxxxx>; linux-clk@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; Leonard Crestez <leonard.crestez@xxxxxxx>;
> Peng Fan <peng.fan@xxxxxxx>
> Subject: [PATCH 2/3] clk: imx: imx8mp: mark sys_pll1/2 as fixed clock
>
> From: Peng Fan <peng.fan@xxxxxxx>
>
> Same to i.MX8MN/i.MX8MM, according Architecture definition guide,
> SYS_PLL1 is fixed at 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use
> imx_clk_fixed to register the clocks and drop code that could change the rate.
>
Better to keep it as PLL for now, we may have the situation that need to power down the PLL in some case.
BR
Jacky Bai
> Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> ---
> drivers/clk/imx/clk-imx8mp.c | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index a85039cfdbf1..77b79f61aab5 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -26,8 +26,6 @@ static const char * const dram_pll_bypass_sels[] =
> {"dram_pll", "dram_pll_ref_se static const char * const
> gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char *
> const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; static const
> char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static
> const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
> -static const char * const sys_pll2_bypass_sels[] = {"sys_pll2",
> "sys_pll2_ref_sel", }; static const char * const sys_pll3_bypass_sels[] =
> {"sys_pll3", "sys_pll3_ref_sel", };
>
> static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out",
> "sys_pll2_500m", @@ -471,8 +469,6 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel",
> anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel",
> anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel",
> anatop_base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> - hws[IMX8MP_SYS_PLL1_REF_SEL] =
> imx_clk_hw_mux("sys_pll1_ref_sel", anatop_base + 0x94, 0, 2, pll_ref_sels,
> ARRAY_SIZE(pll_ref_sels));
> - hws[IMX8MP_SYS_PLL2_REF_SEL] =
> imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels,
> ARRAY_SIZE(pll_ref_sels));
> hws[IMX8MP_SYS_PLL3_REF_SEL] =
> imx_clk_hw_mux("sys_pll3_ref_sel", anatop_base + 0x114, 0, 2, pll_ref_sels,
> ARRAY_SIZE(pll_ref_sels));
>
> hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1",
> "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll); @@ -482,8 +478,8 @@
> static int imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll",
> "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll);
> hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll",
> "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll);
> hws[IMX8MP_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll",
> "arm_pll_ref_sel", anatop_base + 0x84, &imx_1416x_pll);
> - hws[IMX8MP_SYS_PLL1] = imx_clk_hw_pll14xx("sys_pll1",
> "sys_pll1_ref_sel", anatop_base + 0x94, &imx_1416x_pll);
> - hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2",
> "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll);
> + hws[IMX8MP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
> + hws[IMX8MP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
> hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3",
> "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll);
>
> hws[IMX8MP_AUDIO_PLL1_BYPASS] =
> imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1,
> audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),
> CLK_SET_RATE_PARENT); @@ -493,8 +489,6 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_GPU_PLL_BYPASS] =
> imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1,
> gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels),
> CLK_SET_RATE_PARENT);
> hws[IMX8MP_VPU_PLL_BYPASS] =
> imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1,
> vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels),
> CLK_SET_RATE_PARENT);
> hws[IMX8MP_ARM_PLL_BYPASS] =
> imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1,
> arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels),
> CLK_SET_RATE_PARENT);
> - hws[IMX8MP_SYS_PLL1_BYPASS] =
> imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1,
> sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels),
> CLK_SET_RATE_PARENT);
> - hws[IMX8MP_SYS_PLL2_BYPASS] =
> imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1,
> sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels),
> CLK_SET_RATE_PARENT);
> hws[IMX8MP_SYS_PLL3_BYPASS] =
> imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1,
> sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),
> CLK_SET_RATE_PARENT);
>
> hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out",
> "audio_pll1_bypass", anatop_base, 13); @@ -504,8 +498,8 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out",
> "gpu_pll_bypass", anatop_base + 0x64, 11);
> hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out",
> "vpu_pll_bypass", anatop_base + 0x74, 11);
> hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out",
> "arm_pll_bypass", anatop_base + 0x84, 11);
> - hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out",
> "sys_pll1_bypass", anatop_base + 0x94, 11);
> - hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out",
> "sys_pll2_bypass", anatop_base + 0x104, 11);
> + hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out",
> "sys_pll1", anatop_base + 0x94, 11);
> + hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out",
> "sys_pll2",
> +anatop_base + 0x104, 11);
> hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out",
> "sys_pll3_bypass", anatop_base + 0x114, 11);
>
> hws[IMX8MP_SYS_PLL1_40M] =
> imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> --
> 2.16.4
