Hi, Not much to say, On 11/05/2014 at 22:24:35 +0200, Sebastian Hesselbarth wrote : > +* Single-register clock dividers > + > +Single-register clock dividers are complex divider cells, allowing > +to divide a reference clock with a set of fixed dividers. Also they > +comprise and input clock mux with bypass and an ouput clock gate. typo here-----^ > + > +Required properties: > +- compatible: shall be "marvell,berlin2-clk-div" > +- reg: address and length of the corresponding DIV registers > +- #clock-cells: shall be set to 0 > +- clocks: clock specifiers referencing the DIV input clocks > +- clock-names: array of strings describing the clock specifiers above. > + Allowed clock-names are "mux_bypass" for the clock mux bypass selection > + and "muxN" (N=0..7) for each of the 8 possible clock mux inputs. > + -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
