Combophy subsystem provides PHY support to various controllers, viz. PCIe, SATA and EMAC. Adding YAML schemas for the same. Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> --- Changes on v2: Add custom 'select' Pass hardware instance entries with phandles and remove cell-index and bid entries Clock, register address space, are same for the children. So move them to parent node. Two PHY instances cannot run in different modes, so move the phy-mode entry to parent node. Add second child entry in the DT example. .../devicetree/bindings/phy/intel,combo-phy.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,combo-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml new file mode 100644 index 000000000000..8e65a2a71e7f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Combophy Subsystem + +maintainers: + - Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> + +description: | + Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA + controllers. A single Combophy provides two PHY instances. + +# We need a select here so we don't match all nodes with 'simple-bus' +select: + properties: + compatible: + contains: + const: intel,combo-phy + required: + - compatible + +properties: + $nodename: + pattern: "^combophy@[0-9]+$" + + compatible: + items: + - const: intel,combo-phy + - const: simple-bus + + clocks: + description: | + List of phandle and clock specifier pairs as listed + in clock-names property. Configure the clocks according + to the PHY mode. + + reg: + items: + - description: ComboPhy core registers + - description: PCIe app core control registers + + reg-names: + items: + - const: core + - const: app + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: core + + intel,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Chip configuration registers handle and ComboPhy instance id + + intel,hsio: + $ref: /schemas/types.yaml#/definitions/phandle + description: HSIO registers handle and ComboPhy instance id on NOC + + intel,aggregation: + description: | + Specify the flag to confiure ComboPHY in dual lane mode. + type: boolean + + intel,phy-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 + description: | + Configure the mode of the PHY. + 0 - PCIe + 1 - xpcs + 2 - sata + +patternProperties: + "^cb[0-9]phy@[0-9]+$": + type: object + + properties: + compatible: + const: intel,phydev + + "#phy-cells": + const: 0 + + resets: + description: | + reset handle according to the PHY mode. + See ../reset/reset.txt for details. + + required: + - compatible + - "#phy-cells" + +required: + - compatible + - clocks + - reg + - reg-names + - intel,syscfg + - intel,hsio + - intel,phy-mode + +additionalProperties: false + +examples: + - | + combophy@0 { + compatible = "intel,combo-phy", "simple-bus"; + clocks = <&cgu0 1>; + reg = <0xd0a00000 0x40000>, + <0xd0a40000 0x1000>; + reg-names = "core", "app"; + resets = <&rcu0 0x50 6>, + <&rcu0 0x50 17>; + reset-names = "phy", "core"; + intel,syscfg = <&sysconf 0>; + intel,hsio = <&hsiol 0>; + intel,phy-mode = <0>; + + cb0phy0:cb0phy@0 { + compatible = "intel,phydev"; + #phy-cells = <0>; + resets = <&rcu0 0x50 23>; + }; + + cb0phy1:cb0phy@1 { + compatible = "intel,phydev"; + #phy-cells = <0>; + resets = <&rcu0 0x50 24>; + }; + }; -- 2.11.0
