On Wed, Feb 12, 2020 at 02:11:30PM +0800, JC Kuo wrote: > Add support for the XUSB pad controller found on Tegra194 SoCs. It is > mostly similar to the same IP found on Tegra186, but the number of > pads exposed differs, as do the programming sequences. Because most of > the Tegra194 XUSB PADCTL registers definition and programming sequence > are the same as Tegra186, Tegra194 XUSB PADCTL can share the same > driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL. > > Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it > is possible for some platforms have long signal trace that could not > provide sufficient electrical environment for Gen 2 speed. This patch > adds a "maximum-speed" property to usb3 ports which can be used to > specify the maximum supported speed for any particular USB 3.1 port. > For a port that is not capable of SuperSpeedPlus, "maximum-speed" > property should carry "super-speed". > > Signed-off-by: JC Kuo <jckuo@xxxxxxxxxx> > --- > Changes in v6: none > Changes in v5: > - re-use "maximum-speed" instead of adding "nvidia,disable-gen2" > Changes in v4: none > Changes in v3: none > Changes in v2: > - removed unnecessary #if/#endif pairs > - introduce new soc->supports_gen2 flag which indicate whether or not > a soc supports USB 3.1 Gen 2 speed > > drivers/phy/tegra/Makefile | 1 + > drivers/phy/tegra/xusb-tegra186.c | 73 +++++++++++++++++++++++++++++++ > drivers/phy/tegra/xusb.c | 17 +++++++ > drivers/phy/tegra/xusb.h | 5 +++ > 4 files changed, 96 insertions(+) Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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